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the mpc8245 combines a mpc603e core microprocessor with a pci bridge. the pci support on the mpc8245 will allow system designers to rapidly design systems using peripherals already designed for pci and the other standard interfaces. the mpc8245 also integrates a high-performance memory controller which supports various types of rom and sdram. the mpc8245 is the second of a family of products that provides system-level support for industry standard interfaces with a mpc603e processor core. this document describes pertinent electrical and physical characteristics of the mpc8245. for functional characteristics of the processor, refer to the mpc8245 integrated processor users manual (mpc8245um/d). this document contains the following topics: topic page section 1.1, overview 1 section 1.2, features 3 section 1.3, general parameters 5 section 1.4, electrical and thermal characteristics 5 section 1.5, package description 30 section 1.6, pll configuration 37 section 1.7, system design information 42 section 1.8, document revision history 54 section 1.9, ordering information 57 to locate any published errata or updates for this document, refer to the web site at http://www.motorola.com/semiconductors 1.1 overview the mpc8245 integrated processor is comprised of a peripheral logic block and a 32-bit superscalar mpc603e core, as shown in figure 1. advance information mpc8245ec/d rev. 1, 3/2002 mpc8245 integrated processor hardware specifications
2 mpc8245 integrated processor hardware specifications motorola overview figure 1. mpc8245 block diagram peripheral logic instruction unit system integer load/store floating- data instruction 16-kbyte 16-kbyte processor core block processor pll (64-bit) two-instruction fetch (64-bit) two-instruction dispatch 64-bit branch processing unit (bpu) mpc8245 bus register unit (sru) unit (iu) unit (lsu) point unit (fpu) data cache instruction cache mmu mmu additional features: ? prog i/o with watchpoint ? jtag/cop interface ? power management address translator dll fanout buffers pci arbiter message unit (with i 2 o) i 2 c controller dma controller interrupt controller/ epic timers pci bus interface unit memory controller data path ecc controller central control unit 32-bit osc_in five request/grant pairs i 2 c 5 irqs/ peripheral logic block peripheral logic pll pci bus data (64-bit) address data bus (32- or 64-bit) memory/rom/ portx control/address pci interface clocks 16 serial interrupts configuration registers (32-bit) with 8-bit parity or ecc pci_sync_in sdram_sync_in watchpoint facility duart performance monitor sdram clocks
motorola mpc8245 integrated processor hardware specifications 3 features the peripheral logic integrates a pci bridge, dual universal asynchronous receiver/transmitter (duart), memory controller, dma controller, epic interrupt controller, a message unit (and i 2 o interface), and an i 2 c controller. the processor core is a full-featured, high-performance processor with floating-point support, memory management, 16-kbyte instruction cache, 16-kbyte data cache, and power management features. the integration reduces the overall packaging requirements and the number of discrete devices required for an embedded system. the mpc8245 contains an internal peripheral logic bus that interfaces the processor core to the peripheral logic. the core can operate at a variety of frequencies, allowing the designer to trade-off performance for power consumption. the processor core is clocked from a separate pll, which is referenced to the peripheral logic pll. this allows the microprocessor and the peripheral logic block to operate at different frequencies, while maintaining a synchronous bus interface. the interface uses a 64- or 32-bit data bus (depending on memory data bus width) and a 32-bit address bus along with control signals that enable the interface between the processor and peripheral logic to be optimized for performance. pci accesses to the mpc8245 memory space are passed to the processor bus for snooping when snoop mode is enabled. the processor core and peripheral logic are general-purpose in order to serve a variety of embedded applications. the mpc8245 can be used as either a pci host or pci agent controller. 1.2 features major features of the mpc8245 are as follows: ? processor core high-performance, superscalar processor core integer unit (iu), floating-point unit (fpu) (software enabled or disabled), load/store unit (lsu), system register unit (sru), and a branch processing unit (bpu) 16-kbyte instruction cache 16-kbyte data cache lockable l1 cachesentire cache or on a per-way basis up to three of four ways dynamic power managementsupports 60x nap, doze, and sleep modes ? peripheral logic peripheral logic bus C supports various operating frequencies and bus divider ratios C 32-bit address bus, 64-bit data bus C supports full memory coherency C decoupled address and data buses for pipelining of peripheral logic bus accesses C store gathering on peripheral logic bus-to-pci writes memory interface C supports up to 2 gbytes of sdram memory C high-bandwidth data bus (32- or 64-bit) to sdram C programmable timing supporting sdram C supports 1 to 8 banks of 16-, 64-, 128-, 256-, or 512-mbit memory devices C write buffering for pci and processor accesses C supports normal parity, read-modify-write (rmw), or ecc
4 mpc8245 integrated processor hardware specifications motorola features C data-path buffering between memory interface and processor C low-voltage ttl logic (lvttl) interfaces C 272 mbytes of base and extended rom/flash/portx space C base rom space supports 8-bit data path or same size as the sdram data path (32- or 64-bit) C extended rom space supports 8-, 16-, 32-bit gathering data path, 32- or 64-bit (wide) data path C portx: 8-, 16-, 32-, or 64-bit general-purpose i/o port using rom controller interface with programmable address strobe timing, data ready input signal (drdy ), and 4 chip selects 32-bit pci interface C operates up to 66 mhz C pci 2.2-compliant C pci 5.0-v tolerance C support for dual address cycle (dac) for 64-bit pci addressing (master only) C support for pci locked accesses to memory C support for accesses to pci memory, i/o, and configuration spaces C selectable big- or little-endian operation C store gathering of processor-to-pci write and pci-to-memory write accesses C memory prefetching of pci read accesses C selectable hardware-enforced coherency C pci bus arbitration unit (five request/grant pairs) C pci agent mode capability C address translation with two inbound and outbound units (atu) C some internal configuration registers accessible from pci two-channel integrated dma controller (writes to rom/portx not supported) C supports direct mode or chaining mode (automatic linking of dma transfers) C supports scatter gatheringread or write discontinuous memory C 64-byte transfer queue per channel C interrupt on completed segment, chain, and error C local-to-local memory C pci-to-pci memory C local-to-pci memory C pci memory-to-local memory message unit C two doorbell registers C two inbound and two outbound messaging registers Ci 2 o message interface i 2 c controller with full master/slave support that accepts broadcast messages
motorola mpc8245 integrated processor hardware specifications 5 general parameters embedded programmable interrupt controller (epic) C five hardware interrupts (irqs) or 16 serial interrupts C four programmable timers with cascade two (dual) universal asynchronous receiver/transmitters (uarts) integrated pci bus and sdram clock generation programmable pci bus and memory interface output drivers ? system level performance monitor facility ? debug features memory attribute and pci attribute signals debug address signals miv signal: marks valid address and data bus cycles on the memory bus programmable input and output signals with watchpoint capability error injection/capture on data path ieee 1149.1 (jtag)/test interface 1.3 general parameters the following list provides a summary of the general parameters of the mpc8245: technology 0.25 m cmos, five-layer metal die size 49.2 mm 2 transistor count 4.5 million logic design fully static packages surface-mount 352 tape ball grid array (tbga) core power supply: 1.8 v 100 mv dc (only for 266 and 300 mhz parts) 2.0 v 100 mv dc (for 266, 300, 333, and 350 mhz parts) (nominal; see table 2 for details and recommended operating conditions) i/o power supply 3.0 to 3.6 v dc 1.4 electrical and thermal characteristics this section provides the ac and dc electrical specifications and thermal characteristics for the mpc8245. 1.4.1 dc electrical characteristics this section covers ratings, conditions, and other characteristics.
6 mpc8245 integrated processor hardware specifications motorola electrical and thermal characteristics 1.4.1.1 absolute maximum ratings the tables in this section describe the mpc8245 dc electrical characteristics. table 1 provides the absolute maximum ratings. 1.4.1.2 recommended operating conditions table 2 provides the recommended operating conditions for the mpc8245. table 1. absolute maximum ratings characteristic 1 symbol range unit supply voltagecpu core and peripheral logic vdd C0.3 to 2.1 v supply voltagememory bus drivers gvdd C0.3 to 3.6 v supply voltagepci and standard i/o buffers ovdd C0.3 to 3.6 v supply voltageplls avdd/avdd2 C0.3 to 2.1 v supply voltagepci reference lvdd C0.3 to 5.4 v input voltage 2 v in C0.3 to 3.6 v operational die-junction temperature range t j 0 to 105 c storage temperature range t stg C55 to 150 c notes: 1. functional and tested operating conditions are given in table 2. absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. pci inputs with lvdd = 5 v 5% v dc may be correspondingly stressed at voltages exceeding lvdd + 0.5 v dc. table 2. recommended operating conditions characteristic symbol recommended value unit notes supply voltage vdd 1.8 100 mv v 4, 6 2.0 100 mv v 6 i/o buffer supply for pci and standard ovdd 3.3 0.3 v 6 supply voltages for memory bus drivers gvdd 3.3 5% v 8 cpu pll supply voltage avdd 1.8 100 mv v 4, 6 2.0 100 mv v 6 pll supply voltageperipheral logic avdd2 1.8 100 mv v 4, 6 2.0 100 mv v 6 pci reference lvdd 5.0 5% v 2, 9, 10 3.3 0.3 v 3, 9, 10 input voltage pci inputs v in 0 to 3.6 or 5.75 v 2, 3 all other inputs 0 to 3.6 v 5
motorola mpc8245 integrated processor hardware specifications 7 electrical and thermal characteristics figure 2 shows supply voltage sequencing and separation cautions. die-junction temperature t j 0 to 105 c notes: 1. these are the recommended and tested operating conditions. proper device operation outside of these conditions is not guaranteed. 2. pci pins are designed to withstand lvdd + 0.5 v dc when lvdd is connected to a 5.0 v dc power supply. 3. pci pins are designed to withstand lvdd + 0.5 v dc when lvdd is connected to a 3.3 v dc power supply. 4. cpu speed limited to 266 mhz and 300 mhz operation at this voltage. see table 9. cautions: 5. input voltage (v in ) must not be greater than the supply voltage (vdd/avdd/avdd2) by more than 2.5 v at all times including during power-on reset. input voltage (v in ) must not be greater than gvdd/ovdd by more than 0.6 v at all times including during power-on reset. 6. ovdd must not exceed vdd/avdd/avdd2 by more than 1.8 v at any time including during power-on reset. this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 7. vdd/avdd/avdd2 must not exceed ovdd by more than 0.6 v at any time including during power-on reset. this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 8. gvdd must not exceed vdd/avdd/avdd2 by more than 1.8 v at any time including during power-on reset. this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 9. lvdd must not exceed vdd/avdd/avdd2 by more than 5.4 v at any time including during power-on reset. this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 10. lvdd must not exceed ovdd by more than 3.0 v at any time including during power-on reset. this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. table 2. recommended operating conditions (continued) characteristic symbol recommended value unit notes
8 mpc8245 integrated processor hardware specifications motorola electrical and thermal characteristics figure 2. supply voltage sequencing and separation cautions figure 3 shows the undershoot and overshoot voltage of the memory interface of the mpc8245. gvdd_ovdd/(lvdd @ 3.3 v - - - -) vdd/avdd/avdd2 lvdd @ 5 v time 3.3 v 5 v 2.0 v 0 7 10 9 9 10 6,8 dc power supply voltage voltage regulator delay 2 reset configuration pins hrst_cpu , hrst_ctrl pll relock time 3 100 s 9 external memory asserted 255 external memory hrst_cpu , hrst_ctrl vdd stable power supply ramp up 2 see note 1 clock cycles 3 clock cycles setup time 4 vm = 1.4 v maximum rise time must be less than one external memory clock cycle 5 notes: 1. numbers associated with waveform separations correspond to caution numbers listed in table 2. 2. refer to section 1.7.2, power supply sizing for additional information on this topic. 3. refer to table 8 for additional information on pll relock and reset signal assertion timing requirements. 4. refer to table 9 for additional information on reset configuration pin setup timing requirements. 5. hrst_cpu /hrst_ctrl must transition from a logic 0 to a logic 1 in less than one sdram_sync_in clock cycle for the device to be in the nonreset state.
motorola mpc8245 integrated processor hardware specifications 9 electrical and thermal characteristics figure 3. overshoot/undershoot voltage 1.4.1.3 dc electrical characteristics table 3 provides the dc electrical characteristics for the mpc8245 at recommended operating conditions. table 3. dc electrical specifications at recommended operating conditions (see table 2) characteristic condition 3 symbol min max unit input high voltage 1 pci only v ih 0.65 ovdd lvdd v input low voltage pci only v il 0.3 ovdd v input high voltage all other pins (gvdd = 3.3 v) v ih 2.0 3.3 v input low voltage all inputs except pci_sync_in v il gnd 0.8 v pci_sync_in input high voltage cv ih 2.4 v pci_sync_in input low voltage cv il gnd 0.4 v input leakage current 4 for pins using drv_pci driver 0.5 v v in 2.7 v @ lvdd = 4.75 i l 70 a input leakage current 4 all others lvdd = 3.6 v gvdd 3.465 i l 10 a output high voltage i oh = driver dependent 2 (gvdd = 3.3 v) v oh 2.4 v output low voltage i ol = driver dependent 2 (gvdd = 3.3 v) v ol 0.4v gnd/gndring gnd/gndring C 0.3 v gnd/gndring q C 1.0 v not to exceed 10% gvdd_ovdd of t sdram_clk gvdd_ovvdd + 5% 4 v v ih v il
10 mpc8245 integrated processor hardware specifications motorola electrical and thermal characteristics 1.4.1.4 output driver characteristics table 4 provides information on the characteristics of the output drivers referenced in table 16. the values are preliminary estimates from an ibis model and are not tested. capacitance v in = 0 v, f = 1 mhz c in 7.0pf notes: 1. see table 16 for pins with internal pull-up resistors. 2. see table 4 for the typical drive capability of a specific signal pin based on the type of output driver associated with that pin as listed in table 16. 3. these specifications are for the default driver strengths indicated in table 4. 4. leakage current is measured on input and output pins in the high-impedance state. the leakage current is measured for nominal ovdd/lvdd and vdd or both ovdd/lvdd and vdd must vary in the same direction. table 4. drive capability of mpc8245 output pins 5 driver type programmable output impedance ( w ) supply voltage i oh i ol unit notes drv_std_mem 20 ovdd = 3.3 v 36.6 18.0 ma 2, 4, 6 40 (default) 18.6 9.2 ma 2, 4, 6 drv_pci 20 12.0 12.4 ma 1, 3 40 (default) 6.1 6.3 ma 1, 3 drv_mem_ctrl drv_pci_clk drv_mem_clk 6 (default) gvdd = 3.3 v 89.0 42.3 ma 2, 4 20 36.6 18.0 ma 2, 4 40 18.6 9.2 ma 2, 4 notes: 1. for drv_pci, i oh read from the ibis listing in the pull-up mode, i(min) column, at the 0.33 v label by interpolating between the 0.3 v and 0.4 v table entries current values which corresponds to the pci v oh = 2.97 = 0.9 ovdd (ovdd = 3.3 v) where table entry voltage = ovdd C pci v oh . 2. for all others with gvdd or ovdd = 3.3 v, i oh read from the ibis listing in the pull-up mode, i(min) column, at the 0.9 v table entry which corresponds to the v oh = 2.4 v where table entry voltage = gvdd/ovdd C v oh . 3. for drv_pci, i ol read from the ibis listing in the pull-down mode, i(min) column, at 0.33 v = pci v ol = 0 ovdd (ovdd = 3.3 v) by interpolating between the 0.3 v and 0.4 v table entries. 4. for all others with gvdd or ovdd = 3.3 v, i ol read from the ibis listing in the pull-down mode, i(min) column, at the 0.4 v table entry. 5. see driver bit details for output driver control register (0x72) in the mpc8245 integrated processor users manual . 6. see chip errata no. 19 in the mpc8245/mpc8241 risc microprocessor chip errata . table 3. dc electrical specifications (continued) at recommended operating conditions (see table 2) characteristic condition 3 symbol min max unit
motorola mpc8245 integrated processor hardware specifications 11 electrical and thermal characteristics 1.4.1.5 power characteristics table 5 provides preliminary estimated power consumption data for the mpc8245. table 5. preliminary power consumption mode pci bus clock/memory bus clock cpu clock frequency (mhz) unit notes 66/66/ 266 66/133/ 266 66/66/ 300 66/100/ 300 33/83/ 333 66/133/ 333 66/100/ 350 typical 1.5 (1.2) 1.7 (1.3) 1.6 (1.3) 1.7 (1.4) 1.8 2.0 1.9 w 1, 5 maxfp 1.9 (1.5) 2.1 (1.7) 2.0 (1.6) 2.1 (1.7) 2.2 2.4 2.4 w 1, 2 maxint 1.6 (1.3) 1.8 (1.5) 1.7 (1.4) 1.9 (1.5) 1.9 2.1 2.1 w 1, 3 doze 1.0 (0.8) 1.3 (1.0) 1.1 (0.9) 1.3 (1.0) 1.3 1.5 1.4 w 1, 4, 6 nap 0.3 (0.3) 0.5 (0.5) 0.4 (0.3) 0.5 (0.4) 0.4 0.6 0.5 w 1, 4, 6 sleep 0.4 (0.3) 0.2 (0.2) 0.4 (0.3) 0.4 (0.3) 0.2 0.2 0.4 w 1, 4, 6 i/o power supplies 10 mode minimum maximum unit notes typovdd 200 500 mw 7, 8 typgvdd 300 600 mw 7, 9 notes: 1. the values include vdd, avdd, and avdd2 but do not include i/o supply power, see section 1.7.2, power supply sizing, for information on ovdd and gvdd supply power. values shown in parenthesis ( ) indicate power consumption at vdd/avdd/avdd2 = 1.8 v. 2. maximumfp power is measured at vdd = 2.1 v with dynamic power management enabled while running an entirely cache-resident, looping, floating-point multiplication instruction. 3. maximumint power is measured at vdd = 2.1 v with dynamic power management enabled while running entirely cache-resident, looping, integer instructions. 4. power saving mode maximums are measured at vdd = 2.1 v while the device is in doze, nap, or sleep mode. 5. typical power is measured at vdd = avdd = 2.0 v, ovdd = 3.3 v where a nominal fp value, a nominal int value, and a value where there is a continuous flush of cache lines with alternating ones and zeros on 64-bit boundaries to local memory are averaged. 6. power saving mode data measured with only two pci_clks and two sdram_clks enabled. 7. the typical minimum i/o power values were results of the mpc8245 performing cache resident integer operations at the slowest frequency combination of 33:66:200 (pci:mem:cpu) mhz. 8. the typical maximum ovdd value resulted from the mpc8245 operating at the fastest frequency combination of 66:100:350 (pci:mem:cpu) mhz and performing continuous flushes of cache lines with alternating ones and zeros to pci memory. 9. the typical maximum gvdd value resulted from the mpc8245 operating at the fastest frequency combination of 66:100:350 (pci:mem:cpu) mhz and performing continuous flushes of cache lines with alternating ones and zeros on 64-bit boundaries to local memory. 10. power consumption of pll supply pins (avdd and avdd2) < 15 mw. guaranteed by design and is not tested.
12 mpc8245 integrated processor hardware specifications motorola electrical and thermal characteristics 1.4.2 thermal characteristics table 6 provides the package thermal characteristics for the mpc8245. for further information, see section 1.7.9, thermal management information. 1.4.3 ac electrical characteristics this section provides the ac electrical characteristics for the mpc8245. after fabrication, functional parts are sorted by maximum processor core frequency as shown in table 7 and tested for conformance to the ac specifications for that frequency. the processor core frequency is determined by the bus (pci_sync_in) clock frequency and the settings of the pll_cfg[0:4] signals. parts are sold by maximum processor core frequency. see section 1.9, ordering information. table 7 provides the operating frequency information for the mpc8245 at recommended operating conditions (see table 2) with lvdd = 3.3 v 0.3 v. table 6. thermal characterization data characteristic symbol value unit die junction-to-case thermal resistance q jc 1.8 c/w die junction-to-board thermal resistance q jb 4.8 c/w note: refer to section 1.7, system design information, for more details about thermal management . table 7. operating frequency 1 characteristic 2, 3 266 mhz 300 mhz 333 mhz 350 mhz unit vdd/avdd/avdd2 = 1.8/2.0 100 mv vdd/avdd/avdd2 = 2.0 100 mv processor frequency (cpu) 100C266 100C300 100C333 100C350 mhz memory bus frequency 33C133 33C100 4 33C133 33C100 4 mhz pci input frequency 25C66 mhz notes: 1. see part number specification document mpc8245rzupns/d for additional part offering information. 2. caution: the pci_sync_in frequency and pll_cfg[0:4] settings must be chosen such that the resulting peripheral logic/memory bus frequency and cpu (core) frequencies do not exceed their respective maximum or minimum operating frequencies. refer to the pll_cfg[0:4] signal description in section 1.6, pll configuration, for valid pll_cfg[0:4] settings and pci_sync_in frequencies. 3. see table 17 and table 18 for more details on vco limitations for memory and cpu vco frequencies of various pll configurations. 4. there are no available pll_cfg[0:4] settings which support 133 mhz memory interface operation at 300 mhz cpu and 350 mhz operation, since the multipliers do not allow a 300:133 and 350:133 ratio relation. however, running these parts are slower speeds may produce ratios that will run above 100 mhz. see table 17 for the pll settings.
motorola mpc8245 integrated processor hardware specifications 13 electrical and thermal characteristics 1.4.3.1 clock ac specifications table 8 provides the clock ac timing specifications at recommended operating conditions, as defined in section 1.4.3.2, input ac timing specifications these specifications are for the default driver strengths indicated in table 4. table 8. clock ac timing specifications at recommended operating conditions (see table 2) with lvdd = 3.3 v 0.3 v num characteristics and conditions min max unit notes 1a frequency of operation (pci_sync_in) 25 66 mhz 2, 3 pci_sync_in rise and fall times 2.0ns1 4 pci_sync_in duty cycle measured at 1.4 v 40 60 % 5a pci_sync_in pulse width high measured at 1.4 v 6 9 ns 2 5b pci_sync_in pulse width low measured at 1.4 v 6 9 ns 2 7 pci_sync_in jitter 150 ps 8a pci_clk[0:4] skew (pin-to-pin) 250 ps 8b sdram_clk[0:3] skew (pin-to-pin) 190 ps 3 10 internal pll relock time 100 s 2, 4, 5 15 dll lock range with dll_extend = 0 disabled (default) 0 (nt clk C t loop C t fix0 ) 7ns6 16 dll lock range with dll_extend = 1 enabled 0 (nt clk C t clk /2 C t loop C t fix0 ) 7ns 6 17 frequency of operation (osc_in) 25 66 mhz 19 osc_in rise and fall times 5 ns 7 20 osc_in duty cycle measured at 1.4 v 40 60 % 21 osc_in frequency stability 100 ppm notes : 1. rise and fall times for the pci_sync_in input are measured from 0.4 to 2.4 v. 2. specification value at maximum frequency of operation. 3. pin-to-pin skew includes quantifying the additional amount of clock skew (or jitter) from the dll besides any intentional skew added to the clocking signals from the variable length dll synchronization feedback loop, that is, the amount of variance between the internal sys_logic_clk and the sdram_sync_in signal after the dll is locked. while pin-to-pin skew between sdram_clks can be measured, the relationship between the internal sys_logic_clk and the external sdram_sync_in cannot be measured and is guaranteed by design. 4. relock time is guaranteed by design and characterization. relock time is not tested. 5. relock timing is guaranteed by design. pll-relock time is the maximum amount of time required for pll lock after a stable vdd and pci_sync_in are reached during the reset sequence. this specification also applies when the pll has been disabled and subsequently re-enabled during sleep mode. also note that hrst_cpu /hrst_ctrl must be held asserted for a minimum of 255 bus clocks after the pll-relock time during the reset sequence. 6. dll_extend is bit 7 of the pmc2 register <72>. n is a non-zero integer (1 or 2). t clk is the period of one sdram_sync_out clock cycle in ns. t loop is the propagation delay of the dll synchronization feedback loop (pc board runner) from sdram_sync_out to sdram_sync_in in ns; 6.25 inches of loop length (unloaded pc board runner) corresponds to approximately 1 ns of delay. t fix0 is a fixed delay inherent in the design when the dll is at tap point 0 and the dll is contributing no delay; t fix0 equals approximately 3 ns. see figure 5 through figure 8 for dll locking ranges. 7. rise and fall times for the osc_in input is guaranteed by design and characterization. osc_in input rise and fall times are not tested.
14 mpc8245 integrated processor hardware specifications motorola electrical and thermal characteristics figure 4 shows the pci_sync_in input clock timing diagram and figure 5 through figure 8 show the dll locking range loop delay vs. frequency of operation. figure 4. pci_sync_in input clock timing diagram the graphs in figure 5 through figure 8 define the areas of dll locking for various modes. the grey areas represent where the dll will lock. note the following bit descriptions and definitions: ? for standard dll mode (non-extended): clear bit 7 (dll_extend) at offset 0x72 (default). ? for extended dll mode: set bit 7 (dll_extend) at offset 0x72. ? normal tap delay (default): clear bit 2 (dll_max_delay) at offset 0x76. ? max tap delay: set bit 2 (dll_max_delay) at offset 0x76. note also that the dll_max_delay bit can lengthen the amount of time through the delay line. this is accomplished by increasing the time between each of the 128 tap points in the delay line. although this increased time makes it easier to guarantee that the reference clock will be within the dll lock range, it also means there may be slightly more jitter in the output clock of the dll, should the phase comparator shift the clock between adjacent tap points. 5a 5b vm vm = midpoint voltage (1.4 v) 2 3 cv il cv ih 1 pci_sync_in vm vm
motorola mpc8245 integrated processor hardware specifications 15 electrical and thermal characteristics figure 5. dll locking range loop delay vs. frequency of operation for dll_extend=1 and normal tap delay 10 15 20 25 12.5 17.5 22.5 27.5 01234 30 7.5 t loop propagation delay time (ns) t clk sdram_sync_out period (ns)
16 mpc8245 integrated processor hardware specifications motorola electrical and thermal characteristics figure 6. dll locking range loop delay vs. frequency of operation for dll_extend=1 and tap max delay 10 15 20 25 1234 0 12.5 17.5 22.5 27.5 30 7.5 t loop propagation delay time (ns) t clk sdram_sync_out period (ns)
motorola mpc8245 integrated processor hardware specifications 17 electrical and thermal characteristics figure 7. dll locking range loop delay vs. frequency of operation for dll_extend=0 and normal tap delay 01234 12.5 17.5 22.5 10 15 20 25 7.5 t loop propagation delay time (ns) t clk sdram_sync_out period (ns)
18 mpc8245 integrated processor hardware specifications motorola electrical and thermal characteristics figure 8. dll locking range loop delay vs. frequency of operation for dll_extend=0 and max tap delay 12.5 17.5 22.5 1234 10 15 20 25 0 7.5 t loop propagation delay time (ns) t clk sdram_sync_out period (ns)
motorola mpc8245 integrated processor hardware specifications 19 electrical and thermal characteristics 1.4.3.2 input ac timing specifications table 9 provides the input ac timing specifications at recommended operating conditions (see table 2) with lvdd = 3.3 v 0.3 v . see figure 9 and figure 10. table 9. input ac timing specifications num characteristic min max unit notes 10a pci input signals valid to pci_sync_in (input setup) 3.0 ns1,3 10b memory input signals valid to sdram_sync_in (input setup) 10b0 tap 0, register offset <0x77>, bits 5:4 = 0b10 2.6 ns 2, 3, 6 10b1 tap 1, register offset <0x77>, bits 5:4 = 0b11 1.9 10b2 tap 2, register offset <0x77>, bits 5:4 = 0b00 (default) 1.2 10b3 tap 3, register offset <0x77>, bits 5:4 = 0b01 0.5 10c epic, misc. debug input signals valid to sdram_sync_in (input setup) 3.0 ns 2, 3 10d i 2 c input signals valid to sdram_sync_in (input setup) 3.0 ns 2, 3 10e mode select inputs valid to hrst_cpu /h rst_ctrl (input setup) 9 t clk ns2, 3C5 11 t os - sdram_sync_in to sys_logic_clk offset time 0.65 1.0 ns 7 11a sdram_sync_in to memory signal inputs invalid (input hold) 11a0 tap 0, register offset <0x77>, bits 5:4 = 0b10 0 ns 2, 3, 6 11a1 tap 1, register offset <0x77>, bits 5:4 = 0b11 0.7 11a2 tap 2, register offset <0x77>, bits 5:4 = 0b00 (default) 1.4 11a3 tap 3, register offset <0x77>, bits 5:4 = 0b01 2.1 11b hrst_cpu /h rst_ctrl to mode select inputs invalid (input hold) 0 ns 2, 3, 5 11c pci_sync_in to inputs invalid (input hold) 1.0 ns 1, 2, 3 notes: 1. all pci signals are measured from ovdd/2 of the rising edge of pci_sync_in to 0.4 ovdd of the signal in question for 3.3 v pci signaling levels. see figure 10. 2. all memory and related interface input signal specifications are measured from the ttl level (0.8 or 2.0 v) of the signal in question to the vm = 1.4 v of the rising edge of the memory bus clock, sdram_sync_in. sdram_sync_in is the same as pci_sync_in in 1:1 mode, but is twice the frequency in 2:1 mode (processor/memory bus clock rising edges occur on every rising and falling edge of pci_sync_in). see figure 9. 3. input timings are measured at the pin. 4. t clk is the time of one sdram_sync_in clock cycle. 5. all mode select input signals specifications are measured from the ttl level (0.8 or 2.0 v) of the signal in question to the vm = 1.4 v of the rising edge of the hrst_cpu /h rst_ctrl signal. see figure 11. 6. the memory interface input setup and hold times are programmable to four possible combinations by programming bits 5:4 of register offset <0x77> to select the desired input setup and hold times. 7. t os represents a timing adjustment for sdram_sync_in with respect to sys_logic_clk . due to the internal delay present on the sdram_sync_in signal with respect to the sys_logic_clk inputs to the dll, the resulting sdram clocks become offset by the delay amount. the feedback trace length of sdram_sync_out to sdram_sync_in must be shortened by this amount relative to the sdram clock output trace lengths to maintain phase-alignment of the memory clocks with respect to sys_logic_clk .
20 mpc8245 integrated processor hardware specifications motorola electrical and thermal characteristics figure 9. input/output timing diagram referenced to sdram_sync_in . figure 10. input/output timing diagram referenced to pci_sync_in figure 11. input timing diagram for mode select signals 11a vm vm = midpoint voltage (1.4 v) memory 10b-d pci_sync_in inputs/outputs 13b 14b vm vm sdram_sync_in shown in 2:1 mode input timing output timing 12b-d 2.0 v 0.8 v 0.8 v 2.0 v vm ovdd2 10a 11c pci_sync_in pci 12a 13a 14a ovdd2 ovdd2 0.4 ovdd 0.615 ovdd 0.285 ovdd input timing output timing inputs/outputs vm vm = midpoint voltage (1.4 v) 11b mode pins 10e hrst_cpu /hrst_ctrl 2.0 v 0.8 v
motorola mpc8245 integrated processor hardware specifications 21 electrical and thermal characteristics 1.4.3.3 output ac timing specification table 10 provides the processor bus ac timing specifications for the mpc8245 at recommended operating conditions (see table 2) with lvdd = 3.3 v 0.3v. see figure 9. all output timings assume a purely resistive 50- w load (see figure 12). output timings are measured at the pin; time-of-flight delays must be added for trace lengths, vias, and connectors in the system. these specifications are for the default driver strengths indicated in table 4. table 10. output ac timing specifications num characteristic min max unit notes 12a pci_sync_in to output valid, see figure 13 12a0 tap 0, pci_hold_del=00, [mcp ,cke] = 11, 66 mhz pci (default) 6.0 ns 1, 3 12a1 tap 1, pci_hold_del=01, [mcp ,cke] = 10 6.5 12a2 tap 2, pci_hold_del=10, [mcp ,cke] = 01, 33 mhz pci 7.0 12a3 tap 3, pci_hold_del=11, [mcp ,cke] = 00 7.5 12b sdram_sync_in to output valid (memory control and data signals) 4.5 ns 2 12c sdram_sync_in to output valid (for all others) 7.0 ns 2 12d sdram_sync_in to output valid (for i 2 c) 5.0 ns 2 12e sdram_sync_in to output valid (rom/flash/portx) 6.0 ns 2 13a output hold (pci), see figure 13 13a0 tap 0, pci_hold_del=00, [mcp ,cke] = 11, 66 mhz pci (default) 2.0 ns 1, 3, 4 13a1 tap 1, pci_hold_del=01, [mcp ,cke] = 10 2.5 13a2 tap 2, pci_hold_del=10, [mcp ,cke] = 01, 33 mhz pci 3.0 13a3 tap 3, pci_hold_del=11, [mcp ,cke] = 00 3.5 13b output hold (all others) 1.0 ns 2 14a pci_sync_in to output high impedance (for pci) 14.0 ns 1, 3 14b sdram_sync_in to output high impedance (for all others) 4.0 ns 2 notes: 1. all pci signals are measured from gvdd_ovdd/2 of the rising edge of pci_sync_in to 0.285 ovdd or 0.615 ovdd of the signal in question for 3.3 v pci signaling levels. see figure 10. 2. all memory and related interface output signal specifications are specified from the vm = 1.4 v of the rising edge of the memory bus clock, sdram_sync_in to the ttl level (0.8 or 2.0 v) of the signal in question. sdram_sync_in is the same as pci_sync_in in 1:1 mode, but is twice the frequency in 2:1 mode (processor/memory bus clock rising edges occur on every rising and falling edge of pci_sync_in). see figure 9. 3. pci bused signals are composed of the following signals: lock , irdy , c/be [3:0], par, trdy , frame , stop , devsel , perr , serr , ad[31:0], req [4:0], gnt [4:0], idsel , inta . 4. in order to meet minimum output hold specifications relative to pci_sync_in for both 33 and 66 mhz pci systems, the mpc8245 has a programmable output hold delay for pci signals (the pci_sync_in to output valid timing is also affected). the initial value of the output hold delay is determined by the values on the mcp and cke reset configuration signals; the values on these two signals are inverted then stored as the initial settings of pci_hold_del = pmcr2[5:4] (power management configuration register 2 <0x72>), respectively. since mcp and cke have internal pull-up resistors, the default value of pci_hold_del after reset is 0b00. further output hold delay values are available by programming the pci_hold_del value of the pmcr2 configuration register. see figure 13.
22 mpc8245 integrated processor hardware specifications motorola electrical and thermal characteristics figure 12. ac test load for the mpc8245 figure 13. pci_hold_del affect on output valid and hold time output z 0 = 50 w gvdd_ovdd/2 for pci r l = 50 w output measurements are made at the device pin or memory pci_sync_in pci inputs/outputs 33 mhz pci 12a2, 8.1 ns for 33 mhz pci pci_hold_del = 10 12a0, 5.5 ns for 66 mhz pci pci_hold_del = 00 13a2, 2.1 ns for 33 mhz pci pci_hold_del = 10 13a0, 1 ns for 66 mhz pci pci_hold_del = 00 output valid output hold note: diagram not to scale. as pci_hold_del values decrease as pci_hold_del values increase pci inputs and outputs pci inputs/outputs 66 mhz pci ovdd/2 ovdd/2
motorola mpc8245 integrated processor hardware specifications 23 electrical and thermal characteristics 1.4.3.4 i 2 c ac timing specifications table 11 provides the i 2 c input ac timing specifications for the mpc8245 at recommended operating conditions (see table 2) with lvdd = 3.3 v 0.3 v. table 12 provides the i 2 c frequency divider register (i2cfdr) information for the mpc8245. table 11. i 2 c input ac timing specifications num characteristic min max unit notes 1 start condition hold time 4.0 clks1, 2 2 clock low period (time before the mpc8245 will drive scl low as a transmitting slave after detecting scl low as driven by an external master) 8.0 + (16 2 fdr[4:2] ) (5 C 4({fdr[5],fdr[1]} == b10) C 3({fdr[5],fdr[1]} == b11) C 2({fdr[5],fdr[1]} == b00) C 1({fdr[5],fdr[1]} == b01)) clks 1, 2, 4, 5 3 scl/sda rise time (from 0.5 v to 2.4 v) 1 ms 4 data hold time 0 ns 2 5 scl/sda fall time (from 2.4 v to 0.5 v) 1 ms 6 clock high period (time needed to either receive a data bit or generate a start or stop) 5.0 clks 1, 2, 5 7 data setup time 3.0 ns 3 8 start condition setup time (for repeated start condition only) 4.0 clks 1,2 9 stop condition setup time 4.0 clks 1, 2 notes: 1. units for these specifications are in sdram_clk units. 2. the actual values depend on the setting of the digital filter frequency sampling rate (dffsr) bits in the frequency divider register i2cfdr. therefore, the noted timings in the above table are all relative to qualified signals. the qualified scl and sda are delayed signals from what is seen in real time on the i 2 c bus. the qualified scl, sda signals are delayed by the sdram_clk clock times dffsr times 2 plus 1 sdram_clk clock. the resulting delay value is added to the value in the table (where this note is referenced). see figure 15. 3. timing is relative to the sampling clock (not scl). 4. fdr[ x ] refers to the frequency divider register i2cfdr bit x . 5. input clock low and high periods in combination with the fdr value in the frequency divider register (i2cfdr) determine the maximum i 2 c input frequency. see table 12.
24 mpc8245 integrated processor hardware specifications motorola electrical and thermal characteristics table 13 provides the i 2 c output ac timing specifications for the mpc8245 at recommended operating conditions (see table 2) with lvdd = 3.3 v 0.3 v. table 12. mpc8245 maximum i 2 c input frequency fdr hex 2 divider 2 (dec) max i 2 c input frequency 1 sdram_clk @ 33 mhz sdram_clk @ 50 mhz sdram_clk @ 100 mhz 20, 21 160, 192 1.13 mhz 1.72 mhz 3.44 mhz 22, 23, 24, 25 224, 256, 320, 384 733 1.11 mhz 2.22 mhz 0, 1 288, 320 540 819 1.63 mhz 2, 3, 26, 27, 28, 29 384, 448, 480, 512, 640, 768 428 649 1.29 mhz 4, 5 576, 640 302 458 917 6, 7, 2a, 2b, 2c, 2d 768, 896, 960, 1024, 1280, 1536 234 354 709 8, 9 1152, 1280 160 243 487 a, b, 2e, 2f, 30, 31 1536, 1792, 1920, 2048, 2560, 3072 122 185 371 c, d 2304, 2560 83 125 251 e, f, 32, 33, 34, 35 3072, 3584, 3840, 4096, 5120, 6144 62 95 190 10, 11 4608, 5120 42 64 128 12, 13, 36, 37, 38, 39 6144, 7168, 7680, 8192, 10240, 12288 31 48 96 14, 15 9216, 10240 21 32 64 16, 17, 3a, 3b, 3c, 3d 12288, 14336, 15360, 16384, 20480, 24576 16 24 48 18, 19 18432, 20480 10 16 32 1a, 1b, 3e, 3f 24576, 28672, 30720, 32768 81224 1c, 1d 36864, 40960 5 8 16 1e, 1f 49152, 61440 4 6 12 notes: 1. values are in khz unless otherwise specified. 2. fdr hex and divider (dec) values are listed in corresponding order. 3. multiple divider (dec) values will generate the same input frequency, but each divider (dec) value will generate a unique output frequency as shown in table 13.
motorola mpc8245 integrated processor hardware specifications 25 electrical and thermal characteristics figure 14. i 2 c timing diagram i table 13. i 2 c output ac timing specifications num characteristic min max unit notes 1 start condition hold time (fdr[5] == 0) (d fdr /16)/2n + (fdr[5] == 1) (d fdr /16)/2m clks 1, 2, 3 2 clock low period d fdr /2 clks 1, 2, 3 3 scl/sda rise time (from 0.5 v to 2.4 v) ms4 4 data hold time 8.0 + (16 2 fdr[4:2] ) (5 C 4({fdr[5],fdr[1]} == b10) C 3({fdr[5],fdr[1]} == b11) C 2({fdr[5],fdr[1]} == b00) C 1({fdr[5],fdr[1]} == b01)) clks 1, 2, 3 5 scl/sda fall time (from 2.4 v to 0.5 v) < 5ns5 6 clock high time d fdr /2 clks 1, 2, 3 7 data setup time (mpc8245 as a master only) (d fdr /2) C (output data hold time) clks 1, 3 8 start condition setup time (for repeated start condition only) d fdr + (output start condition hold time) clks 1, 2, 3 9 stop condition setup time 4.0 clks 1, 2 notes: 1. units for these specifications are in sdram_clk units. 2. the actual values depend on the setting of the digital filter frequency sampling rate (dffsr) bits in the frequency divider register i2cfdr. therefore, the noted timings in the above table are all relative to qualified signals. the qualified scl and sda are delayed signals from what is seen in real time on the i 2 c bus. the qualified scl, sda signals are delayed by the sdram_clk clock times dffsr times 2 plus 1 sdram_clk clock. the resulting delay value is added to the value in the table (where this note is referenced). see figure 15. 3. d fdr is the decimal divider number indexed by fdr[5:0] value. refer to table 10-5 in the mpc8245 integrated processor users manual. fdr[x] refers to the frequency divider register i2cfdr bit x . n is equal to a variable number that would make the result of the divide (data hold time value) equal to a number less than 16. m is equal to a variable number that would make the result of the divide (data hold time value) equal to a number less than 9. 4. since scl and sda are open-drain type outputs, which the mpc8245 can only drive low, the time required for scl or sda to reach a high level depends on external signal capacitance and pull-up resistor values. 5. specified at a nominal 50 pf load. scl sda vm vm 6 2 1 4
26 mpc8245 integrated processor hardware specifications motorola electrical and thermal characteristics figure 15. i 2 c timing diagram ii figure 16. i 2 c timing diagram iii . figure 17. i 2 c timing diagram iv (qualified signal) 1.4.3.5 epic serial interrupt mode ac timing specifications table 14 provides the epic serial interrupt mode ac timing specifications for the mpc8245 at recommended operating conditions (see table 2) with gvdd = 3.3 v 5% and lvdd = 3.3 v 0.3 v. scl sda vm v l v h 9 8 3 5 input data valid dffsr filter clock sda 7 note: dffsr filter clock is the sdram_clk clock times dffsr value. scl/sda realtime vm scl/sda qualified vm delay note: the delay is the local memory clock times dffsr times 2 plus 1 local memory clock.
motorola mpc8245 integrated processor hardware specifications 27 electrical and thermal characteristics figure 18. epic serial interrupt mode output timing diagram figure 19. epic serial interrupt mode input timing diagram table 14. epic serial interrupt mode ac timing specifications num characteristic min max unit notes 1 s_clk frequency 1/14 sdram_sync_in 1/2 sdram_sync_in mhz 1 2 s_clk duty cycle 40 60 % 3 s_clk output valid time 6 ns 4 output hold time 0 ns 5s_frame , s_rst output valid time 1 sys_logic_clk period + 6 ns 2 6 s_int input setup time to s_clk 1 sys_logic_clk period + 2 ns 2 7 s_int inputs invalid (hold time) to s_clk 0ns2 notes: 1. see the mpc8245 integrated processor users manual for a description of the epic interrupt control register (eicr) describing s_clk frequency programming. 2. s_rst, s_frame , and s_int shown in figure 18 and figure 19, depict timing relationships to sys_logic_clk and s_clk and do not describe functional relationships between s_rst, s_frame , and s_int. see the mpc8245 integrated processor users manual for a complete description of the functional relationships between these signals. 3. the sys_logic_clk waveform is the clocking signal of the internal peripheral logic from the output of the peripheral logic pll; sys_logic_clk is the same as sdram_sync_in when the sdram_sync_out to sdram_sync_in feedback loop is implemented and the dll is locked. see the mpc8245 integrated processor users manual for a complete clocking description. s_clk s_rst vm vm vm s_frame sys_logic_clk 3 vm vm vm vm 4 3 5 4 6 s_clk s_int 7 vm
28 mpc8245 integrated processor hardware specifications motorola electrical and thermal characteristics 1.4.3.6 ieee 1149.1 (jtag) ac timing specifications table 15 provides the jtag ac timing specifications for the mpc8245 while in the jtag operating mode at recommended operating conditions (see table 2) with lvdd = 3.3 v 0.3 v. timings are independent of the system clock (pci_sync_in). figure 20. jtag clock input timing diagram figure 21. jtag trst timing diagram table 15. jtag ac timing specification (independent of pci_sync_in) num characteristic min max unit notes tck frequency of operation 0 25 mhz 1 tck cycle time 40 ns 2 tck clock pulse width measured at 1.5 v 20 ns 3 tck rise and fall times 0 3 ns 4trst setup time to tck falling edge 10 ns 1 5trst assert time 10 ns 6 input data setup time 5 ns 2 7 input data hold time 15 ns 2 8 tck to output data valid 0 30 ns 3 9 tck to output high impedance 0 30 ns 3 10 tms, tdi data setup time 5 ns 11 tms, tdi data hold time 15 ns 12 tck to tdo data valid 0 15 ns 13 tck to tdo high impedance 0 15 ns notes: 1. trst is an asynchronous signal. the setup time is for test purposes only. 2. nontest (other than tdi and tms) signal input timing with respect to tck. 3. nontest (other than tdo) signal output timing with respect to tck. tck 2 2 1 vm vm vm 3 3 vm = midpoint voltage 4 5 trst tck
motorola mpc8245 integrated processor hardware specifications 29 electrical and thermal characteristics figure 22. jtag boundary scan timing diagram figure 23. test access port timing diagram 6 7 input data valid 8 9 output data valid tck data inputs data outputs data outputs 10 11 input data valid 12 13 output data valid tck tdi, tms tdo tdo
30 mpc8245 integrated processor hardware specifications motorola package description 1.5 package description this section details package parameters, pin assignments, and dimensions. 1.5.1 package parameters for the mpc8245 the mpc8245 uses a 35 mm 35 mm, cavity up, 352-pin plastic ball grid array (pbga) package. the package parameters are as follows. package outline 35 mm 35 mm interconnects 352 pitch 1.27mm solder balls 62sn/36pb/2ag solder ball diameter 0.75 mm maximum module height 1.65 mm co-planarity specification 0.15 mm maximum force 6.0 lbs. total, uniformly distributed over package (8 grams/ball) 1.5.2 pin assignments and package dimensions figure 24 shows the top surface, side profile, and pinout of the mpc8245, 352 pbga package.
motorola mpc8245 integrated processor hardware specifications 31 package description figure 24. mpc8245 package dimensions and pinout assignments b a c C e C C f C 0.150 C t C t h g 25 23 21 19 17 15 13 11 9 7 5 3 1 a c e g j l n r u w aa ac ae 352x ? d min max a 34.8 35.2 b 34.8 35.2 c 1.45 1.65 d .60 .90 g 1.27 basic h .85 .95 k 31.75 basic l .50 .70 top view notes: 26 24 22 20 18 16 14 12 10 8 6 4 2 b d f h k m p t v y ab ad af corner k l bottom view 1. drawing not to scale. 2. all measurements are in millimeters (mm) . k
32 mpc8245 integrated processor hardware specifications motorola package description 1.5.3 pinout listings table 16 provides the pinout listing for the mpc8245, 352 tbga package. table 16. mpc8245 pinout listing name pin number type power supply output driver type notes pci interface signals c/be [3:0] p25 k23 f23 a25 i/o ovdd drv_pci 6, 15 devsel h26 i/o3 ovdd drv_pci 8, 15 frame j24 i/o ovdd drv_pci 8, 15 irdy k25 i/o ovdd drv_pci 8, 15 lock j26 input ovdd 8 ad[31:0] v25 u25 u26 u24 u23 t25 t26 r25 r26 n26 n25 n23 m26 m25 l25 l26 f24 e26 e25 e23 d26 d25 c26 a26 b26 a24 b24 d19 b23 b22 d22 c22 i/o3 ovdd drv_pci 6, 15 par g25 i/o ovdd drv_pci 15 gnt [3:0] w25 w24 w23 v26 output ovdd drv_pci 6, 15 gnt4 /da5 w26 output ovdd drv_pci 7, 15, 14 req [3:0] y25 aa26 aa25 ab26 input ovdd 6, 12 req4 /da4 y26 i/o ovdd 12, 14 perr g26 i/o ovdd drv_pci 8, 15, 18 serr f26 i/o ovdd drv_pci 8, 15, 16 stop h25 i/o ovdd drv_pci 8, 15 trdy k26 i/o ovdd drv_pci 8, 15 inta ac26 output ovdd drv_pci 15, 16 idsel p26 input ovdd memory interface signals mdl[0:31] ad17 ae17 ae15 af15 ac14 ae13 af13 af12 af11 af10 af9 ad8 af8 af7 af6 ae5 b1 a1 a3 a4 a5 a6 a7 d7 a8 b8 a10 d10 a12 b11 b12 a14 i/o gvdd drv_std_mem 5, 6
motorola mpc8245 integrated processor hardware specifications 33 package description mdh[0:31] ac17 af16 ae16 ae14 af14 ac13 ae12 ae11 ae10 ae9 ae8 ac7 ae7 ae6 af5 ac5 e4 a2 b3 d4 b4 b5 d6 c6 b7 c9 a9 b10 a11 a13 b13 a15 i/o gvdd drv_std_mem 6 dqm[0:7] ab1 ab2 k3 k2 ac1 ac2 k1 j1 output gvdd drv_mem_ctrl 6 cs [0:7] y4 aa3 aa4 ac4 m2 l2 m1 l1 output gvdd drv_mem_ctrl 6 foe h1 i/o gvdd drv_mem_ctrl 3, 4 rcs0 n4 output gvdd drv_mem_ctrl 3, 4 rcs1 n2 output gvdd drv_mem_ctrl rcs2 /trig_in af20 i/o ovdd 10, 14 rcs3 /trig_out ac18 output gvdd drv_mem_ctrl 14 sdma[1:0] w1 w2 i/o gvdd drv_mem_ctrl 3, 4, 6 sdma[11:2] n1 r1 r2 t1 t2 u4 u2 u1 v1 v3 output gvdd drv_mem_ctrl 6 drdy b20 input ovdd 9, 14 sdma12/sreset b16 i/o gvdd drv_mem_ctrl 10, 14 sdma13/tben b14 i/o gvdd drv_mem_ctrl 10, 14 sdma14/ chkstop_in d14 i/o gvdd drv_mem_ctrl 10, 14 sdba1 p1 output gvdd drv_mem_ctrl sdba0 p2 output gvdd drv_mem_ctrl par[0:7] af3 ae3 g4 e2 ae4 af4 d2 c2 i/o gvdd drv_std_mem 6 sdras ad1 output gvdd drv_mem_ctrl 3 sdcas ad2 output gvdd drv_mem_ctrl 3 cke h2 output gvdd drv_mem_ctrl 3, 4 we aa1 output gvdd drv_mem_ctrl as y1 output gvdd drv_mem_ctrl 3, 4 epic control signals irq0/s_int c19 input ovdd irq1/s_clk b21 i/o ovdd drv_pci irq2/s_rst ac22 i/o ovdd drv_pci table 16. mpc8245 pinout listing (continued) name pin number type power supply output driver type notes
34 mpc8245 integrated processor hardware specifications motorola package description irq3/s_frame ae24 i/o ovdd drv_pci irq4/l_int a23 i/o ovdd drv_pci i 2 c control signals sda ae20 i/o ovdd drv_std_mem 10, 16 scl af21 i/o ovdd drv_std_mem 10, 16 duart control signals sout1/pci_clk0 ac25 output gvdd drv_pci_clk 13, 14 sin1/pci_clk1 ab25 i/o gvdd drv_pci_clk 13, 14 sout2/rts1 / pci_clk2 ae26 output gvdd drv_pci_clk 13, 14 sin2/cts1 / pci_clk3 af25 i/o gvdd drv_pci_clk 13, 14 clock-out signals pci_clk0/sout1 ac25 output gvdd drv_pci_clk 13, 14 pci_clk1/sin1 ab25 i/o gvdd drv_pci_clk 13, 14 pci_clk2/rts1 / sout2 ae26 output gvdd drv_pci_clk 13, 14 pci_clk3/cts1 / sin2 af25 i/o gvdd drv_pci_clk 13, 14 pci_clk4/da3 af26 output gvdd drv_pci_clk 13, 14 pci_sync_out ad25 output gvdd drv_pci_clk pci_sync_in ab23 input gvdd sdram_clk [0:3] d1 g1 g2 e1 output gvdd drv_mem_ctrl or drv_mem_clk 6, 21 sdram_sync_out c1 output gvdd drv_mem_ctrl or drv_mem_clk 21 sdram_sync_in h3 input gvdd cko/da1 b15 output ovdd drv_std_mem 14 osc_in ad21 input ovdd 19 miscellaneous signals hrst_ctrl a20 input ovdd hrst_cpu a19 input ovdd mcp a17 output ovdd drv_std_mem 3, 4, 17 table 16. mpc8245 pinout listing (continued) name pin number type power supply output driver type notes
motorola mpc8245 integrated processor hardware specifications 35 package description nmi d16 input ovdd smi a18 input ovdd 10 sreset /sdma12 b16 i/o gvdd drv_mem_ctrl 10, 14 tben/sdma13 b14 i/o gvdd drv_mem_ctrl 10, 14 qack /da0 f2 output ovdd drv_std_mem 3, 4, 14 chkstop_in / sdma14 d14 i/o gvdd drv_mem_ctrl 10, 14 trig_in/rcs2 af20 i/o ovdd 10, 14 trig_out/rcs3 ac18 output gvdd drv_mem_ctrl 14 maa[0:2] af2 af1 ae1 output gvdd drv_std_mem 3, 4, 6 miv a16 output ovdd 24 pmaa[0:1] ad18 af18 output ovdd drv_std_mem 3, 4, 6, 15 pmaa[2] ae19 output ovdd drv_std_mem 4, 6, 15 test/configuration signals pll_cfg[0:4]/ da[10:6] a22 b19 a21 b18 b17 i/o ovdd drv_std_mem 6, 14, 20 test0 ad22 input ovdd 1, 9 drdy b20 input ovdd 9, 10, 14 rtc y2 input gvdd 11 tck af22 input ovdd 9, 12 tdi af23 input ovdd 9, 12 tdo ac21 output ovdd 24 tms ae22 input ovdd 9, 12 trst ae23 input ovdd 9, 12 power and ground signals gnd aa2 aa23 ac12 ac15 ac24 ac3 ac6 ac9 ad11 ad14 ad16 ad19 ad23 ad4 ae18 ae2 ae21 ae25 b2 b25 b6 b9 c11 c13 c16 c23 c4 c8 d12 d15 d18 d21 d24 d3 f25 f4 h24 j25 j4 l24 l3 m23 m4 n24 p3 r23 r4 t24 t3 v2 v23 w3 ground table 16. mpc8245 pinout listing (continued) name pin number type power supply output driver type notes
36 mpc8245 integrated processor hardware specifications motorola package description lvdd ac20 ac23 d20 d23 g23 p23 y23 reference voltage 3.3 v, 5.0 v lvdd gvdd ab3 ab4 ac10 ac11 ac8 ad10 ad13 ad15 ad3 ad5 ad7 c10 c12 c3 c5 c7 d13 d5 d9 e3 g3 h4 k4 l4 n3 p4 r3 u3 v4 y3 power for memory drivers 3.3 v gvdd ovdd ab24 ad20 ad24 c14 c20 c24 e24 g24 j23 k24 m24 p24 t23 y24 pci / stnd 3.3 v ovdd vdd aa24 ac16 ac19 ad12 ad6 ad9 c15 c18 c21 d11 d8 f3 h23 j3 l23 m3 r24 t4 v24 w4 power for core 1.8/2.0 v vdd 22 no connect d17 23 avdd c17 power for pll (cpu core logic) 1.8/2.0 v avdd 22 avdd2 af24 power for pll (peripheral logic) 1.8/ 2.0 v avdd2 22 debug/manufacturing pins da0/qack f2 output ovdd drv_std_mem 3, 4, 14 da1/cko b15 output ovdd drv_std_mem 14 da2 c25 output ovdd drv_pci 2 da3/pci_clk4 af26 output gvdd drv_pci_clk 14 da4/req4 y26 i/o ovdd 12, 14 da5/gnt4 w26 output ovdd drv_pci 7, 15, 14 da[10:6]/ pll_cfg[0:4] a22 b19 a21 b18 b17 i/o ovdd drv_std_mem 6, 14, 20 da[11] ad26 output ovdd drv_pci 2 da[12:13] af17 af19 output ovdd drv_std_mem 2, 6 table 16. mpc8245 pinout listing (continued) name pin number type power supply output driver type notes
motorola mpc8245 integrated processor hardware specifications 37 pll configuration 1.6 pll configuration the internal plls of the mpc8245 are configured by the pll_cfg[0:4] signals. for a given pci_sync_in (pci bus) frequency, the pll configuration signals set both the peripheral logic/memory bus pll (vco) frequency of operation for the pci-to-memory frequency multiplying and the mpc603e cpu pll (vco) frequency of operation for memory-to-cpu frequency multiplying. the pll configurations for the mpc8245 is shown in table 17 and table 18. da[14:15] f1 j2 output gvdd drv_mem_ctrl 2, 6 notes: 1. place a pull-up resistor of 120 w or less on the test0 pin. 2. treat these pins as no connects (nc) unless using debug address functionality. 3. this pin has an internal pull-up resistor which is enabled only when the mpc8245 is in the reset state. the value of the internal pull-up resistor is not guaranteed, but is sufficient to ensure that a logic 1 is read into configuration bits during reset. 4. this pin is a reset configuration pin. 5. dl[0] is a reset configuration pin and has an internal pull-up resistor which is enabled only when the mpc8245 is in the reset state. the value of the internal pull-up resistor is not guaranteed, but is sufficient to ensure that a logic 1 is read into configuration bits during reset. 6. multi-pin signals such as ad[31:0] or mdl[0:31] have their physical package pin numbers listed in order, corresponding to the signal names. example: ad0 is on pin c22, ad1 is on pin d22, ..., ad31 is on pin v25. 7. gnt4 is a reset configuration pin and has an internal pull-up resistor which is enabled only when the mpc8245 is in the reset state. 8. recommend a weak pull-up resistor (2 k w C10 k w ) be placed on this pci control pin to lvdd. 9. v ih and v il for these signals are the same as the pci v ih and v il entries in table 3. 10. recommend a weak pull-up resistor (2 k w C10 k w ) be placed on this pin to ovdd. 11. recommend a weak pull-up resistor (2 k w C10 k w ) be placed on this pin to gvdd. 12. this pin has an internal pull-up resistor which is enabled at all times. the value of the internal pull-up resistor is not guaranteed, but is sufficient to prevent unused inputs from floating. 13. external pci clocking source or fan-out buffer may be required for system if using the mpc8245 duart functionality since pci_clk[0:3] are not available in duart mode. only pci_clk4 is available in duart mode. 14. this pin is a multiplexed signal and appears more than once in this table. 15. this pin is affected by programmable pci_hold_del parameter. 16. this pin is an open drain signal. 17. this pin can be programmed to be driven (default) or can be programmed (in pmcr2) to be open drain. 18. this pin is a sustained three-state pin as defined by the pci local bus specification. 19. osc_in utilizes the 3.3 v pci interface driver which is 5 v tolerant, see table 2 for details. 20. pll_cfg[0:4] signals are sampled a few clocks after the negation of hrst_cpu and hrst_ctrl . 21. sdram_clk[0:3] and sdram_sync_out signals use drv_mem_ctrl for chip rev 1.1 (a). these signals use drv_mem_clk for chip rev 1.2 (b). 22. the 266 and 300 mhz part offerings can be ran at a source voltage of 1.8 100 mv or 2.0 100 mv. note that source voltage should be 2.0 100 mv for 333- and 350-mhz parts. 23. this pin was formally lavdd on the mpc8240. it is a no connect on the mpc8245. this should not pose a problem when replacing an mpc8240 with an mpc8245. 24. the driver capability of this pin is hardwired to 40 w and cannot be changed. table 16. mpc8245 pinout listing (continued) name pin number type power supply output driver type notes
38 mpc8245 integrated processor hardware specifications motorola pll configuration table 17. pll configurations (266- and 300-mhz parts) ref pll_ cfg [0:4] 10,13 266 mhz part 9 300 mhz part 9 multipliers pci clock input (pci_ sync_in) range 1 (mhz) periph logic/ mem bus clock range (mhz) cpu clock range (mhz) pci clock input (pci_ sync_in) range 1 (mhz) periph logic/ mem bus clock range (mhz) cpu clock range (mhz) pci to mem (mem vco) mem to cpu (cpu vco) 0 00000 12 25 - 35 5 75 - 105 188 - 263 25 - 40 5 75 - 120 188 - 300 3 (2) 2.5 (2) 1 00001 12 25 - 29 5 75 - 88 225 - 264 25 - 33 5 75 - 99 225 - 297 3 (2) 3 (2) 2 00010 11 50 18 - 59 5 50 - 59 225 - 266 50 18 - 66 1 50 - 66 225 - 297 1 (4) 4.5 (2) 300011 11,14 50 4 - 66 1 50 - 66 100 - 133 50 4 - 66 1 50 - 66 100 - 133 1 (bypass) 2 (4) 4 00100 12 25 - 46 4 50 - 92 100 - 184 25 - 46 4 50 - 92 100 - 184 2 (4) 2 (4) 5 00101 reserved reserved note 20 6 00110 15 bypass bypass bypass 700111 14 60 6 - 66 1 60 - 66 180 - 198 60 6 - 66 1 60 - 66 180 - 198 1 (bypass) 3 (2) 8 01000 12 60 6 - 66 1 60 - 66 180 - 198 60 6 - 66 1 60 - 66 180 - 198 1 (4) 3 (2) 9 01001 19 45 6 - 66 1 90 - 132 180 - 264 45 6 - 66 1 90 - 132 180 - 264 2 (2) 2 (2) a 01010 12 25 - 29 5 50 - 58 225 - 261 25 - 33 5 50 - 66 225 - 297 2 (4) 4.5 (2) b 01011 19 45 3 - 59 5 68 - 88 204 - 264 45 3 - 66 1 68 - 99 204 - 297 1.5 (2) 3 (2) c01100 12 36 6 - 46 4 72 - 92 180 - 230 36 6 - 46 4 72 - 92 180 - 230 2 (4) 2.5 (2) d01101 19 45 3 - 50 5 68 - 75 238 - 263 45 3 - 57 5 68 - 85 238 - 298 1.5 (2) 3.5 (2) e 01110 12 30 6 - 44 5 60 - 88 180 - 264 30 6 - 46 4 60 - 92 180 - 276 2 (4) 3 (2) f 01111 19 25 5 75 263 25 - 28 5 75 - 85 263 - 298 3 (2) 3.5 (2) 10 10000 12 30 6 - 44 2,5 60 - 132 180 - 264 30 6 - 44 2 60 - 132 180 - 264 3 (2) 2 (2) 11 10001 19 25 - 26 5 100 - 106 250 - 266 25 - 29 2 100 - 116 250 - 290 4 (2) 2.5 (2) 12 10010 12 60 6 - 66 1 90 - 99 180 - 198 60 6 - 66 1 90 - 99 180 - 198 1.5 (2) 2 (2) 13 10011 19 not available 25 2 100 300 4 (2) 3 (2) 14 10100 12 26 6 - 38 5 52 - 76 182 - 266 26 6 - 42 5 52 - 84 182 - 294 2 (4) 3.5 (2) 15 10101 19 not available 27 3 - 30 5 68 - 75 272 - 300 2.5 (2) 4 (2) 16 10110 12 25 - 33 5 50 - 66 200 - 264 25 - 37 5 50 - 74 200 - 296 2 (4) 4 (2) 17 10111 19 25 - 33 5 100 - 132 200 - 264 25 - 33 2 100 - 132 200 - 264 4 (2) 2 (2) 18 11000 12 27 3 - 35 5 68 - 88 204 - 264 27 3 - 40 5 68 - 100 204 - 300 2.5 (2) 3 (2) 19 11001 19 36 6 - 53 5 72 - 106 180 - 265 36 6 - 59 2 72 - 118 180 - 295 2 (2) 2.5 (2) 1a 11010 12 50 18 - 66 1 50 - 66 200 - 264 50 18 - 66 1 50 - 66 200 - 264 1 (4) 4 (2) 1b 11011 19 33 6 - 44 5 66 - 88 198 - 264 33 6 - 50 5 66 - 100 198 - 300 2 (2) 3 (2) 1c 11100 12 44 6 - 59 5 66 - 88 198 - 264 44 6 - 66 1 66 - 99 198 - 297 1.5 (2) 3 (2)
motorola mpc8245 integrated processor hardware specifications 39 pll configuration 1d 11101 12 48 6 - 66 1 72 - 99 180 - 248 48 6 - 66 1 72 - 99 180 - 248 1.5 (2) 2.5 (2) 1e 11110 8 not usable not usable off off 1f 11111 8 not usable not usable off off notes: 1. limited by maximum pci input frequency (66 mhz). 2 limited by maximum system memory interface operating frequency (100 mhz @ 350 mhz cpu). 3. limited by minimum memory vco frequency (133 mhz). 4. limited due to maximum memory vco frequency (372 mhz). 5. limited by maximum cpu operating frequency (266 mhz). 6. limited by minimum cpu vco frequency (360 mhz). 7. limited by maximum cpu vco frequency (800 mhz). 8. in clock off mode, no clocking occurs inside the mpc8245 regardless of the pci_sync_in input. 9. range values are shown rounded down to the nearest whole number (decimal place accuracy removed) for clarity. 10. pll_cfg[0:4] settings not listed (01011, 01101, 01111, 10001, 10011, 10101, 11001, and 11011) are reserved. 11. multiplier ratios for this pll_cfg[0:4] setting are different from the mpc8240 and are not backwards-compatible. 12. pci_sync_in range for this pll_cfg[0:4] setting is different from the mpc8240 and may not be fully backwards-compatible. 13. bits 7C 4 of register offset <0xe2> contain the pll_cfg[0:4] setting value. 14. in pll bypass mode, the pci_sync_in input signal clocks the internal processor directly, the peripheral logic pll is disabled, and the bus mode is set for 1:1 (pci:mem) mode operation. this mode is intended for hardware modeling support. the ac timing specifications given in this document do not apply in pll bypass mode. 15. in dual pll bypass mode, the pci_sync_in input signal clocks the internal peripheral logic directly, the peripheral logic pll is disabled, and the bus mode is set for 1:1 (pci_sync_in:mem) mode operation. in this mode, the osc_in input signal clocks the internal processor directly in 1:1 (osc_in:cpu) mode operation, and the processor pll is disabled. the pci_sync_in and osc_in input clocks must be externally synchronized. this mode is intended for hardware modeling support. the ac timing specifications given in this document do not apply in dual pll bypass mode. 16. limited by maximum system memory interface operating frequency (133 mhz @ 266 mhz cpu). 17. limited by minimum cpu operating frequency (100 mhz). 18. limited by minimum memory bus frequency (50 mhz). 19. pci_sync_in range for this pll_cfg[0:4] setting does not exist on the mpc8240 and may not be fully backwards-compatible. 20. no longer supported. table 17. pll configurations (266- and 300-mhz parts) (continued) ref pll_ cfg [0:4] 10,13 266 mhz part 9 300 mhz part 9 multipliers pci clock input (pci_ sync_in) range 1 (mhz) periph logic/ mem bus clock range (mhz) cpu clock range (mhz) pci clock input (pci_ sync_in) range 1 (mhz) periph logic/ mem bus clock range (mhz) cpu clock range (mhz) pci to mem (mem vco) mem to cpu (cpu vco)
40 mpc8245 integrated processor hardware specifications motorola pll configuration table 18. pll configurations (333- and 350-mhz parts) ref pll_ cfg [0:4] 10,13 333 mhz part 9 350 mhz part 9 multipliers pci clock input (pci_ sync_in) range 1 (mhz) periph logic/ mem bus clock range (mhz) cpu clock range (mhz) pci clock input (pci_ sync_in) range 1 (mhz) periph logic/ mem bus clock range (mhz) cpu clock range (mhz) pci to mem (mem vco) mem to cpu (cpu vco) 0 00000 12 25 - 44 16 75 - 132 188 - 330 25 - 44 16 75 - 132 188 - 330 3 (2) 2.5 (2) 1 00001 12 25 - 37 5 75 - 111 225 - 333 25 - 38 5 75 - 114 225 - 342 3 (2) 3 (2) 2 00010 11 50 18 - 66 1 50 - 66 225 - 297 50 18 - 66 1 50 - 66 225 - 297 1 (4) 4.5 (2) 300011 11,14 50 4 - 66 1 50 - 66 100 - 133 50 4 - 66 1 50 - 66 100 - 133 1 (bypass) 2 (4) 4 00100 12 25 - 46 4 50 - 92 100 - 184 25 - 46 4 50 - 92 100 - 184 2 (4) 2 (4) 5 00101 reserved reserved note 20 6 00110 15 bypass bypass bypass 700111 14 60 6 - 66 1 60 - 66 180 - 198 60 6 - 66 1 60 - 66 180 - 198 1 (bypass) 3 (2) 8 01000 12 60 6 - 66 1 60 - 66 180 - 198 60 6 - 66 1 60 - 66 180 - 198 1 (4) 3 (2) 9 01001 19 45 6 - 66 1 90 - 132 180 - 264 45 6 - 66 1 90 - 132 180 - 264 2 (2) 2 (2) a 01010 12 25 - 37 5 50 - 74 225 - 333 25 - 38 5 50 - 76 225 - 342 2 (4) 4.5 (2) b 01011 19 45 3 - 66 1 68 - 99 204 - 297 45 3 - 66 1 68 - 99 204 - 297 1.5 (2) 3 (2) c01100 12 36 6 - 46 4 72 - 92 180 - 230 36 6 - 46 4 72 - 92 180 - 230 2 (4) 2.5 (2) d01101 19 45 3 - 63 5 68 - 95 238 - 333 45 3 - 66 1 68 - 99 238 - 347 1.5 (2) 3.5 (2) e 01110 12 30 6 - 46 4 60 - 92 180 - 276 30 6 - 46 4 60 - 92 180 - 276 2 (4) 3 (2) f 01111 19 25 - 31 5 75 - 93 263 - 326 25 - 33 5 75 - 99 263 - 347 3 (2) 3.5 (2) 10 10000 12 30 6 - 44 2 60 - 132 180 - 264 30 6 - 44 2 60 - 132 180 - 264 3 (2) 2 (2) 11 10001 19 25 - 33 2 100 - 132 250 - 330 25 - 33 2 100 - 132 250 - 330 4 (2) 2.5 (2) 12 10010 12 60 6 - 66 1 90 - 99 180 - 198 60 6 - 66 1 90 - 99 180 - 198 1.5 (2) 2 (2) 13 10011 19 25 - 27 5 100 - 108 300 - 324 25 - 29 5 100 - 116 300 - 348 4 (2) 3 (2) 14 10100 12 26 6 - 47 4 52 - 94 182 - 329 26 6 - 47 4 52 - 94 182 - 329 2 (4) 3.5 (2) 15 10101 19 27 3 - 33 5 68 - 83 272 - 332 27 3 - 34 5 68 - 85 272 - 340 2.5 (2) 4 (2) 16 10110 12 25 - 41 5 50 - 82 200 - 328 25 - 43 5 50 - 86 200 - 344 2 (4) 4 (2) 17 10111 19 25 - 33 2 100 - 132 200 - 264 25 - 33 2 100 - 132 200 - 264 4 (2) 2 (2) 18 11000 12 27 3 - 44 5 68 - 110 204 - 330 27 3 - 46 5 68 - 115 204 - 345 2.5 (2) 3 (2) 19 11001 19 36 6 - 66 1 72 - 132 180 - 330 36 6 - 66 1 72 - 132 180 - 330 2 (2) 2.5 (2) 1a 11010 12 50 18 - 66 1 50 - 66 200 - 264 50 18 - 66 1 50 - 66 200 - 264 1 (4) 4 (2) 1b 11011 19 33 6 - 55 5 66 - 110 198 - 330 33 6 - 58 5 66 - 116 198 - 348 2 (2) 3 (2)
motorola mpc8245 integrated processor hardware specifications 41 pll configuration 1c 11100 12 44 6 - 66 1 66 - 99 198 - 297 44 6 - 66 1 66 - 99 198 - 297 1.5 (2) 3 (2) 1d 11101 12 48 6 - 66 1 72 - 99 180 - 248 48 6 - 66 1 72 - 99 180 - 248 1.5 (2) 2.5(2) 1e 11110 8 not usable not usable off off 1f 11111 8 not usable not usable off off notes: 1. limited by maximum pci input frequency (66 mhz). 2. limited by maximum system memory interface operating frequency (100 mhz @ 350 mhz cpu). 3. limited by minimum memory vco frequency (133 mhz). 4. limited due to maximum memory vco frequency (372 mhz). 5. limited by maximum cpu operating frequency (266 mhz). 6. limited by minimum cpu vco frequency (360 mhz). 7. limited by maximum cpu vco frequency (800 mhz). 8. in clock off mode, no clocking occurs inside the mpc8245 regardless of the pci_sync_in input. 9. range values are shown rounded down to the nearest whole number (decimal place accuracy removed) for clarity. 10. pll_cfg[0:4] settings not listed (01011, 01101, 01111, 10001, 10011, 10101, 11001, and 11011) are reserved. 11. multiplier ratios for this pll_cfg[0:4] setting are different from the mpc8240 and are not backwards-compatible. 12. pci_sync_in range for this pll_cfg[0:4] setting is different from the mpc8240 and may not be fully backwards-compatible. 13. bits 7 C4 of register offset <0xe2> contain the pll_cfg[0:4] setting value. 14. in pll bypass mode, the pci_sync_in input signal clocks the internal processor directly, the peripheral logic pll is disabled, and the bus mode is set for 1:1 (pci:mem) mode operation. this mode is intended for hardware modeling support. the ac timing specifications given in this document do not apply in pll bypass mode. 15. in dual pll bypass mode, the pci_sync_in input signal clocks the internal peripheral logic directly, the peripheral logic pll is disabled, and the bus mode is set for 1:1 (pci_sync_in:mem) mode operation. in this mode, the osc_in input signal clocks the internal processor directly in 1:1 (osc_in:cpu) mode operation, and the processor pll is disabled. the pci_sync_in and osc_in input clocks must be externally synchronized. this mode is intended for hardware modeling support. the ac timing specifications given in this document do not apply in dual pll bypass mode. 16. limited by maximum system memory interface operating frequency (133 mhz @ 333 mhz cpu). 17. limited by minimum cpu operating frequency (100 mhz). 18. limited by minimum memory bus frequency (50 mhz). 19. pci_sync_in range for this pll_cfg[0:4] setting does not exist on the mpc8240 and may not be fully backwards-compatible. 20. no longer supported. table 18. pll configurations (333- and 350-mhz parts) (continued) ref pll_ cfg [0:4] 10,13 333 mhz part 9 350 mhz part 9 multipliers pci clock input (pci_ sync_in) range 1 (mhz) periph logic/ mem bus clock range (mhz) cpu clock range (mhz) pci clock input (pci_ sync_in) range 1 (mhz) periph logic/ mem bus clock range (mhz) cpu clock range (mhz) pci to mem (mem vco) mem to cpu (cpu vco)
42 mpc8245 integrated processor hardware specifications motorola system design information 1.7 system design information this section provides electrical and thermal design recommendations for successful application of the mpc8245. 1.7.1 pll power supply filtering the avdd and avdd2 power signals are provided on the mpc8245 to provide power to the peripheral logic/memory bus pll and the mpc603e processor pll. to ensure stability of the internal clocks, the power supplied to the avdd and avdd2 input signals should be filtered of any noise in the 500 khz to 10 mhz resonant frequency range of the plls. two separate circuits similar to the one shown in figure 25 using surface mount capacitors with minimum effective series inductance (esl) is recommended for avdd and avdd2 power signal pins. consistent with the recommendations of dr. howard johnson in high speed digital design: a handbook of black magic (prentice hall, 1993), multiple small capacitors of equal value are recommended over using multiple values. the circuits should be placed as close as possible to the respective input signal pins to minimize noise coupled from nearby circuits. routing directly as possible from the capacitors to the input signal pins with minimal inductance of vias is important. figure 25. pll power supply filter circuit 1.7.2 power supply sizing the power consumption numbers provided in table 5 do not reflect power from the ovdd and gvdd power supplies which are non-negligible for the mpc8245. in typical application measurements, the ovdd power ranged from 200 to 500 mw and the gvdd power ranged from 300 to 600 m w. the ranges low-end power numbers were results of the mpc8245 performing cache resident integer operations at the slowest frequency combination of 33:66:200 (pci:mem:cpu) mhz. the ovdd high end ranges value resulted from the mpc8245 operating at the fastest frequency combination of 66:100:350 (pci:mem:cpu) mhz and performing continuous flushes of cache lines with alternating ones and zeros to pci memory. the gvdd high-end ranges value resulted from the mpc8245 operating at the fastest frequency combination of 66:100:350 (pci:mem:cpu) mhz and performing continuous flushes of cache lines with alternating ones and zeros on 64-bit boundaries to local memory. 1.7.3 decoupling recommendations due to its dynamic power management feature, the large address and data buses, and its high operating frequencies, the mpc8245 can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. this noise must be prevented from reaching other components in the mpc8245 system, and the mpc8245 itself requires a clean, tightly regulated source of power. therefore, it is recommended that the system designer place at least one decoupling capacitor at each vdd, ovdd, gvdd, and lvdd pin of the mpc8245. it is also recommended that these decoupling capacitors receive their power from separate vdd, ovdd, gvdd, and gnd power planes in the pcb, utilizing short vdd avdd or avdd2 2.2 f 2.2 f gnd low esl surface mount capacitors 10 w
motorola mpc8245 integrated processor hardware specifications 43 system design information traces to minimize inductance. these capacitors should have a value of 0.1 f. only ceramic smt (surface mount technology) capacitors should be used to minimize lead inductance, preferably 0508 or 0603, oriented such that connections are made along the length of the part. in addition, it is recommended that there be several bulk storage capacitors distributed around the pcb, feeding the vdd, ovdd, gvdd, and lvdd planes, to enable quick recharging of the smaller chip capacitors. these bulk capacitors should have a low esr (equivalent series resistance) rating to ensure the quick response time necessary. they should also be connected to the power and ground planes through two vias to minimize inductance. suggested bulk capacitors: 100C330 f (avx tps tantalum or sanyo oscon). 1.7.4 connection recommendations to ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. unused active-low inputs should be tied to ovdd. unused active-high inputs should be connected to gnd. all nc (no connect) signals must remain unconnected. power and ground connections must be made to all external vdd, ovdd, gvdd, lvdd, and gnd pins of the mpc8245. the pci_sync_out signal is intended to be routed halfway out to the pci devices and then returned to the pci_sync_in input of the mpc8245. the sdram_sync_out signal is intended to be routed halfway out to the sdram devices and then returned to the sdram_sync_in input of the mpc8245. the trace length may be used to skew or adjust the timing window as needed. see motorola application notes an1849/d and an2164/d for more information on this topic. note that there is an sdram_sync_in to pci_sync_in time requirement. (see table 9.) 1.7.5 pull-up/pull-down resistor requirements the data bus input receivers are normally turned off when no read operation is in progress; therefore, they do not require pull-up resistors on the bus. the data bus signals are: mdh[0:31], mdl[0:31], and par[0:7]. if the 32-bit data bus mode is selected, the input receivers of the unused data and parity bits (mdl[0:31] and par[4:7]) will be disabled, and their outputs will drive logic zeros when they would otherwise normally be driven. for this mode, these pins do not require pull-up resistors and should be left unconnected by the system to minimize possible output switching. the test0 pin requires a pull-up resistor of 120 w or less connected to ovdd. it is recommended that rtc have weak pull-up resistors (2 k w C10 k w ) connected to gvdd_ovdd. it is recommended that the following signals be pulled up to ovdd with weak pull-up resistors (2 k w C10 k w ): sda, scl, smi , sreset /sdma12, tben/sdma13, chkstop_in /sdma14, trig_in/rcs2 , and drdy it is recommended that the following pci control signals be pulled up to lvdd with weak pull-up resistors (2 k w C10 k w ): devsel , frame , irdy , lock , perr , serr , stop , and trdy . the resistor values may need to be adjusted stronger to reduce induced noise on specific board designs. the following pins have internal pull-up resistors enabled at all times: req [3:0], req4 /da4, tck, tdi, tms, and trst . see table 16 for more information.
44 mpc8245 integrated processor hardware specifications motorola system design information the following pins have internal pull-up resistors enabled only while device is in the reset state: gnt4 /da5, mdl0, foe , rcs0 , sdras , sdcas , cke, as , mcp , maa[0:2], pmaa[0:2], and qack /da0. see table 16 for more information. the following pins are reset configuration pins: gnt4 /da5, mdl[0], foe , rcs0 , cke, as , mcp , qack /da0, maa[0:2], pmaa[0:2], sdma[1:0], mdh[16:31], and pll_cfg[0:4]/da[10:15]. these pins are sampled during reset to configure the device. the pll_cfg[0:4] signals are sampled a few clocks after the negation of hrst_cpu and hrst_ctrl. reset configuration pins should be tied to gnd via 1-k w pull-down resistors to ensure a logic zero level is read into the configuration bits during reset if the default logic-one level is not desired. any other unused active low input pins should be tied to a logic-one level via weak pull-up resistors (2 k w C10 k w ) to the appropriate power supply listed in table 16. unused active high input pins should be tied to gnd via weak pull-down resistors (2 k w C10 k w ). 1.7.6 pci reference voltage lvdd the mpc8245 p ci reference voltage (lvdd) pins should be connected to 3.3 0.3 v power supply if interfacing the mpc8245 into a 3.3-v pci bus system. similarly, the lvdd pins should be connected to 5.0 v 5% power supply if interfacing the mpc8245 into a 5-v pci bus system. for either reference voltage, the mpc8245 always performs 3.3-v signaling as described in the pci local bus specification (rev. 2.2). the mpc8245 tolerates 5-v signals when interfaced into a 5-v pci bus system. 1.7.7 mpc8245 compatibility with mpc8240 the mpc8245 ac timing specifications are backwards-compatible with those of the mpc8240, except for the requirements of item 11 in table 9. timing adjustments are needed as specified for t os (sdram_sync_in to sys_logic_clk offset) time requirements. the mpc8245 does not support the sdram flow-through memory interface. the nominal core vdd power supply changes from 2.5 v on the mpc8240 to 1.8/2.0 v on the mpc8245. see table 2 for details. the mpc8245 pll_cfg[0:4] setting 0x02 (0b00010) has a different pci to mem and mem to cpu multiplier ratio than the same setting on the mpc8240, and thus, is not backwards-compatible. see table 17 for details. the mpc8245 pll_cfg[0:4] settings 0x08 (0b01000), 0x0c (0b01100), 0x12 (0b10010), 0x18 (0b11000), 0x1c (0b11100), and 0x1d (0b11101) are capable of accepting a subset of the pci_sync_in input frequency range of that of the mpc8240, and thus, may not be fully backwards-compatible. see table 17 for details. there are two additional reset configuration signals on the mpc8245 which are not used as reset configuration signals on the mpc8240: sdma0 and sdma1. the sdma0 reset configuration pin selects between the mpc8245 duart or the mpc8240 backwards compatible mode pci_clk[0:4] functionality on these multiplexed signals. the default state (logic 1) of sdma0 selects the mpc8240 backwards compatible mode of pci_clk[0:4] functionality while a logic 0 state on the sdma0 signal selects duart functionality. note if using the duart mode, four of the five pci clocks, pci_clk[0:3], are not available.
motorola mpc8245 integrated processor hardware specifications 45 system design information the sdma1 reset configuration pin selects between mpc8245 extended rom functionality or mpc8240 backwards-compatible functionality on the multiplexed signals: tben, chkstop_in , sreset , trig_in, and trig_out. the default state (logic 1) of sdma1 selects the mpc8240 backwards compatible mode functionality, while a logic 0 state on the sdma1 signal selects extended rom functionality. note if using the extended rom mode, tben, chkstop_in , sreset , trig_in, and trig_out functionality are not available. the driver names and capability of the pins for the mpc8245 and that of the mpc8240 vary slightly. please refer to the drive capability table (for the odcr register at 0x73) in the mpc8240 integrated processor hardware specifications and table 4 for more details. the programmable pci output valid and output hold feature controlled by bits in the power management configuration register 2 (pmcr2) <0x72> has changed slightly in the mpc8245. for the mpc8240, three bits, pmcr2[6:4] = pci_hold_del, are used to select one of eight possible pci output timing configurations. pmcr2[6:5] are software controllable but initially are set by the reset configuration state of the mcp and cke signals, respectively; pmcr2[4] can be changed by software. the default configuration for pmcr2[6:4] = 0b110 since the mcp and cke signals have internal pull-up resistors, but this default configuration does not select 33 or 66 mhz pci operation output timing parameters for the mpc8240; this choice is made by software. for the mpc8245, only 2 bits in the power management configuration register 2 (pmcr2), pmcr2[5:4] = pci_hold_del, control the variable pci output timing. pmcr2[5:4] are software controllable but initially are set by the inverted reset configuration state of the mcp and cke signals, respectively. the default configuration for pmcr2[5:4] = 0b00 since the mcp and cke signals have internal pull-up resistors and the values from these signals are inverted; this default configuration selects 66 mhz pci operation output timing parameters. there are four programmable pci output timing configurations on the mpc8245, see table 10 for details. voltage sequencing requirements for the mpc8245 are similar to those for the mpc8240; however, there are two changes which are applicable for the mpc8245. first, there is an additional requirement for the mpc8245 that the non-pci input voltages (v in ) must not be greater than gvdd or ovdd by more than 0.6 v at all times including during power-on reset (see caution 5 in table 2). second, for the mpc8245, lvdd must not exceed ovdd by more than 3.0 v at any time including during power-on reset (see caution 10 in table 2); the allowable separation between lvdd and ovdd is 3.6 v for the mpc8240. there is no lavdd input voltage supply signal on the mpc8245 since the sdram clock delay-locked loop (dll) has power supplied internally. signal d17 should be treated as a no connect for the mpc8245. 1.7.8 jtag configuration signals boundary scan testing is enabled through the jtag interface signals. the trst signal is optional in the ieee 1149.1 specification, but is provided on all processors that implement the powerpc architecture. while it is possible to force the tap controller to the reset state using only the tck and tms signals, more reliable power-on reset performance will be obtained if the trst signal is asserted during power-on reset. because the jtag interface is also used for accessing the common on-chip processor (cop) function, simply tying trst to hreset is not practical. the cop function of these processors allows a remote computer system (typically, a pc with dedicated hardware and debugging software) to access and control the internal operations of the processor. the cop interface connects primarily through the jtag port of the processor, with some additional status monitoring signals. the cop port requires the ability to independently assert hreset or trst in order to fully control the processor. if the target system has independent reset sources, such as voltage monitors, watchdog timers, power supply failures, or push-button switches, then the cop reset signals must be merged into these signals with logic.
46 mpc8245 integrated processor hardware specifications motorola system design information the arrangement shown in figure 26 allows the cop to independently assert hreset or trst , while ensuring that the target can drive hreset as well. if the jtag interface and cop header will not be used, trst should be tied to hreset so that it is asserted when the system reset signal (hreset ) is asserted ensuring that the jtag scan chain is initialized during power-on. the cop header shown in figure 26 adds many benefitsbreakpoints, watchpoints, register and memory examination/modification, and other standard debugger features are possible through this interfaceand can be as inexpensive as an unpopulated footprint for a header to be added when needed. the cop interface has a standard header for connection to the target system, based on the 0.025" square-post, 0.100" centered header assembly (often called a berg header). there is no standardized way to number the cop header shown in figure 26; consequently, many different pin numbers have been observed from emulator vendors. some are numbered top-to-bottom then left-to-right, while others use left-to-right then top-to-bottom, while still others number the pins counter clockwise from pin 1 (as with an ic). regardless of the numbering, the signal placement recommended in figure 26 is common to all known emulators.
motorola mpc8245 integrated processor hardware specifications 47 system design information figure 26. cop connector diagram hreset hrst_cpu hrst_ctrl from target board sources 3 13 9 5 1 6 10 2 15 11 7 16 12 8 4 key no pin hreset 13 sreset sreset sreset 6 nc nc nc 11 vdd_sense 6 5 2 15 3 1 k w 10 k w 10 k w 10 k w ovdd ovdd ovdd ovdd chkstop_in chkstop_in 7 8 tms tdo tdi tck tms tdo tdi tck 9 1 3 4 trst 7 16 2 10 12 (if any) cop header 14 4 key cop connector physical pin out notes: 1. qack is an output on the mpc8245 and is not required at the cop header for emulation. 2. run/stop normally found on pin 5 of the cop header is not implemented on the mpc8245. connect pin 5 of the cop header to ovdd with a 1- k w pull-up resistor. 3. ckstp_out normally found on pin 15 of the cop header is not implemented on the mpc8245. connect pin 15 of the cop header to ovdd with a 10-k w pull-up resistor. 4. pin 14 is not physically present on the cop header. qack 1 ovdd ovdd 10 k w ovdd gnd 5. component not populated. trst 10 k w ovdd 10 k w 10 k w 6. sreset functions as output sdma12 in extended rom mode. 7. chkstop_in functions as output sdma14 in extended rom mode. mpc8245
48 mpc8245 integrated processor hardware specifications motorola system design information 1.7.9 thermal management information this section provides thermal management information for the tape ball grid array (tbga) package for air-cooled applications. depending on the application environment and the operating frequency, heat sinks may be required to maintain junction temperature within specifications. proper thermal control design is primarily dependent upon the system-level design: the heat sink, airflow, and thermal interface material. to reduce the die-junction temperature, heat sinks may be attached to the package by several methods: adhesive, spring clip to holes in the printed-circuit board or package, or mounting clip and screw assembly; see figure 27. figure 27. package exploded cross-sectional view with several heat sink options figure 28 depicts the die junction-to-ambient thermal resistance for four typical cases: ? a heat sink is not attached to the tbga package and there exists a high board-level thermal loading from adjacent components. ? a heat sink is not attached to the tbga package and there exists a low board-level thermal loading from adjacent components. ? a heat sink (for example, chipcoolers #hts255-p) is attached to the pbga package and there exists high board-level thermal loading from adjacent components. ? a heat sink (for example, chipcoolers #hts255-p) is attached to the tbga package and there exists low board-level thermal loading from adjacent components. adhesive or thermal interface heat sink tbga package heat sink clip printed-circuit board option material die
motorola mpc8245 integrated processor hardware specifications 49 system design information figure 28. die junction-to-ambient resistance the board designer can choose between several types of heat sinks to place on the mpc8245. there are several commercially available heat sinks for the mpc8245 provided by the following vendors: aavid thermalloy 603-224-9988 80 commercial st. concord, nh 03301 internet: www.aavidthermalloy.com alpha novatech 408-749-7601 473 sapena ct. #15 santa clara, ca 95054 internet: www.alphanovatech.com the bergquist company 800-347-4572 18930 west 78 th st. chanhassen, mn 55317 internet: www.bergquistcompany.com international electronic research corporation (ierc) 818-842-7277 413 north moss st. burbank, ca 91502 internet: www.ctscorp.com 2 4 6 8 10 12 14 16 18 0 0.5 1 1.5 2 2.5 die junction-to-ambient thermal resistance ( c/w) airflow velocity (m/s) no heat sink and high thermal board-level loading of adjacent components no heat sink and low thermal board-level loading of adjacent components attached heat sink and high thermal board-level loading of adjacent components attached heat sink and low thermal board-level loading of adjacent components
50 mpc8245 integrated processor hardware specifications motorola system design information tyco electronics 800-522-6752 chip coole rs? p.o. box 3668 harrisburg, pa 17105-3668 internet: www.chipcoolers.com wakefield engineering 603-635-5102 33 bridge st. pelham, nh 03076 internet: www.wakefield.com ultimately, the final selection of an appropriate heat sink depends on many factors, such as thermal performance at a given air velocity, spatial volume, mass, attachment method, assembly, and cost. other heat sinks offered by aavid thermalloy, alpha novatech, the bergquist company, ierc, chip coolers, and wakefield engineering offer different heat sink-to-ambient thermal resistances, and may or may not need airflow. 1.7.9.1 internal package conduction resistance for the tbga, cavity down, packaging technology, shown in figure 29, the intrinsic conduction thermal resistance paths are as follows: ? the die junction-to-case thermal resistance ? the die junction-to-ball thermal resistance figure 29 depicts the primary heat transfer path for a package with an attached heat sink mounted to a printed-circuit board. figure 29. pbga package with heat sink mounted to a printed-circuit board for this die-up, wire-bond pbga package, heat generated on the active side of the chip is conducted mainly through the mold cap, the heat sink attach material (or thermal interface material), and finally through the heat sink where it is removed by forced-air convection. external resistance external resistance internal resistance (note the internal versus external package resistance) radiation convection radiation convection heat sink printed-circuit board thermal interface material die/substrate/c5 solder balls die junction mold cap
motorola mpc8245 integrated processor hardware specifications 51 system design information 1.7.9.2 adhesives and thermal interface materials a thermal interface material is recommended between the top of the mold cap and the bottom of the heat sink to minimize the thermal contact resistance. for those applications where the heat sink is attached by spring clip mechanism, figure 30 shows the thermal performance of three thin-sheet thermal-interface materials (silicone, graphite/oil, floroether oil), a bare joint, and a joint with thermal grease as a function of contact pressure. as shown, the performance of these thermal interface materials improves with increasing contact pressure. the use of thermal grease significantly reduces the interface thermal resistance. that is, the bare joint results in a thermal resistance approximately seven times greater than the thermal grease joint. heat sinks are attached to the package by means of a spring clip to holes in the printed-circuit board (see figure 30). therefore, the synthetic grease offers the best thermal performance, considering the low interface pressure. of course, the selection of any thermal interface material depends on many factors: thermal performance requirements, manufacturability, service temperature, dielectric properties, cost, etc. figure 30. thermal performance of select thermal interface material the board designer can choose between several types of thermal interface. heat sink adhesive materials should be selected based upon high conductivity, yet adequate mechanical strength to meet equipment shock/vibration requirements. there are several commercially-available thermal interfaces and adhesive materials provided by the following vendors: chomerics, inc. 781-935-4850 77 dragon ct. woburn, ma 01888-4014 internet: www.chomerics.com 0 0.5 1 1.5 2 0 1020304050607080 silicone sheet (0.006 in.) bare joint floroether oil sheet (0.007 in.) graphite/oil sheet (0.005 in.) synthetic grease contact pressure (psi) specific thermal resistance (k-in. 2 /w)
52 mpc8245 integrated processor hardware specifications motorola system design information dow-corning corporation 800-248-2481 dow-corning electronic materials 2200 w. salzburg rd. midland, mi 48686-0997 internet: www.dow.com shin-etsu microsi, inc. 888-642-7674 10028 s. 51st st. phoenix, az 85044 internet: www.microsi.com thermagon inc. 888-246-9050 4707 detroit ave. cleveland, oh 44102 internet: www.thermagon.com 1.7.9.3 heat sink usage an estimation of the chip junction temperature, t j , can be obtained from the equation: t j = t a + (r q ja x p d ) where t a = ambient temperature for the package ( c) r q ja = junction-to-ambient thermal resistance ( c/w) p d = power dissipation in the package (w) the junction-to-ambient thermal resistance is an industry-standard value that provides a quick and easy estimation of thermal performance. unfortunately, two values are in common usage: the value determined on a single layer board and the value obtained on a board with two planes. for packages such as the pbga, these values can be different by a factor of two. which value is closer to the application depends on the power dissipated by other components on the board. the value obtained on a single layer board is appropriate for the tightly packed printed-circuit board. the value obtained on the board with the internal planes is usually appropriate if the board has low power dissipation and the components are well separated. when a heat sink is used, the thermal resistance is expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: r q ja = r q jc + r q ca where r q ja = junction-to-ambient thermal resistance ( c/w) r q jc = junction-to-case thermal resistance ( c/w) r q ca = case-to-ambient thermal resistance ( c/w) r q jc is device-related and cannot be influenced by the user. the user controls the thermal environment to change the case-to-ambient thermal resistance, r q ca . for instance, the user can change the size of the heat sink, the air flow around the device, the interface material, the mounting arrangement on the printed-circuit board, or the thermal dissipation on the printed-circuit board surrounding the device. to determine the junction temperature of the device in the application when heat sinks are not used, the thermal characterization parameter ( q jt ) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using the following equation: t j = t t + ( q jt p d )
motorola mpc8245 integrated processor hardware specifications 53 system design information where: t t = thermocouple temperature atop the package ( c) q jt = thermal characterization parameter ( c/w) p d = power dissipation in package (w) the thermal characterization parameter is measured per jesd51-2 specification using a 40-gauge type t thermocouple epoxied to the top center of the package case. the thermocouple should be positioned so that the thermocouple junction rests on the package. a small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the junction. the thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. when a heat sink is used, the junction temperature is determined from a thermocouple inserted at the interface between the case of the package and the interface material. a clearance slot or hole is normally required in the heat sink. minimizing the size of the clearance is important to minimize the change in thermal performance caused by removing part of the thermal interface to the heat sink. because of the experimental difficulties with this technique, many engineers measure the heat sink temperature and then back calculate the case temperature using a separate measurement of the thermal resistance of the interface. from this case temperature, the junction temperature is determined from the junction-to-case thermal resistance. in many cases, it is appropriate to simulate the system environment using a computational fluid dynamics thermal simulation tool. in such a tool, the simplest thermal model of a package which has demonstrated reasonable accuracy (about 20%) is a two-resistor model consisting of a junction-to-board and a junction-to-case thermal resistance. the junction-to-case covers the situation where a heat sink will be used or where a substantial amount of heat is dissipated from the top of the package. the junction-to-board thermal resistance describes the thermal performance when most of the heat is conducted to the printed-circuit board. 1.7.10 references semiconductor equipment and materials international 805 east middlefield rd. mountain view, ca 94043 (415) 964-5111 mil-spec and eia/jesd (jedec) specifications are available from global engineering documents at 800-854-7179 or 303-397-7956. jedec specifications are available on the web at http://www.jedec.org.
54 mpc8245 integrated processor hardware specifications motorola document revision history 1.8 document revision history table 19 provides a revision history for this hardware specification. table 19. revision history table revision no. substantive change(s) 0.0 initial release. 0.1 made vdd/avdd/avdd2 = 1.8 v 100 mv information for 133 mhz memory interface operation to section 1.3, table 2, table 5, table 9, table 17, and section 1.7.2. pin d17, formerly lavdd (supply voltage for dll), is a no connect on the mpc8245 since the dll voltage is supplied internally. eliminated all references to lavdd; updated section 1.7.1. previous note 4 of table 2 did not apply to the mpc8245 (mpc8240 document legacy). new note 4 added in reference to max cpu speed at reduced vdd voltage. updated the programmable output impedance of dev_mem_addr in table 4 to 6 w to reflect characterization data. updated table 5 to reflect reduced power consumption when operating vdd/avdd/avdd2 = 1.8 v 100 mv. changed notes 2, 3, and 4 to reflect vdd at 1.9 v. changed note 5 to represent vdd = avdd = 1.8 v. updated table 7 to reflect vdd/avdd/avdd2 voltage level operating frequency dependencies; changed 250 mhz device column to 266 mhz; modified note 1 eliminating vco references; added note 2. changed 250 mhz processor frequency offering to 266 mhz. changed spec 12b for memory output valid time in table 10 from 5.5 ns to 4.5 ns; this is a key specification change to enable 133 mhz memory interface designs. updated pinout table 16 with the following changes: ? pin types for rcs0 , rcs3 /trig_out and da[11:15] were erroneously listed as i/o, changed pin types to output. ? pin types for req4 /da4, rcs2 /trig_in, and pll_cfg[0:4]/da[10:6] were erroneously listed as input, changed pin types to i/o. ? changed pin d17 from lavdd to no connect; deleted note 21 and references. ? notes 3, 5, and 7 contained references to the mpc8240 (mpc8240 document legacy); changed these references to mpc8245. ? previous notes 13 and 14 did not apply to the mpc8245 (mpc8240 document legacy), these notes were deleted; moved note 19 to become new note 13; moved note 20 to become new note 14; updated associated references. ? added note 3 to sdma[1:0] signals about internal pull-up resistors during reset state. ? reversed vector ordering for the pci interface signals: c/be [0:3] changed to c/be [3:0], ad[0:31] changed to ad[31:0], gnt [0:3] changed to gnt [3:0], and req [0:3] changed to req [3:0]. the package pin number orderings were also reversed meaning that pin functionality did not change. for example, ad0 is still on signal c22, ad1 is still on signal d22, ..., ad31 is still on signal v25. this change was made to make the vectored pci signals in this hardware specification consistent with the pci local bus specification and the mpc8245 integrated processor users manual vector ordering. ? changed test1 /drdy signal on pin b20 to drdy . ? changed test2 signal on pin y2 to rtc for performance monitor use. updated pll table 17 with the following changes for 133 mhz memory interface operation: ? added ref. 9 (01001) and ref. 17 (10111) details; removed these settings from note 10 (reserved settings list). ? enhanced range of ref. 10 (10000). ? updated note 13, changed bits 16C20 erroneous information to correct bits 23C19. ? added notes 16 and 17. added information to section 1.7.8, in reference to chkstop_in and sreset not being available in extended rom mode.
motorola mpc8245 integrated processor hardware specifications 55 document revision history 0.2 changed core supply voltage to 2.0 100 mv in section 1.3. (supply voltage of 1.8 100 mv is no longer recommended.) changed rows 2, 5, and 6 of table 2 to 2.0 100 mv in the recommended value column. changed the power consumption numbers in table 5 to reflect the power values for vdd = 2.0 v. (notes 2, 3, 4, and 5 of the table were also updated to reflect the new value of vdd.) updated table 9 for vdd/avdd/avdd2 to 2.0 100 mv. table 8: vdd/avdd/avdd2 was changed to 2.0 v for both cpu frequency offerings. note 2 was updated by removing the at reduced voltage... statement. table 10: update maximum time of the rows 12a0 through 12a3. table 16: fixed overbars for the active-low signals. changed pin type information for vdd, avdd, and avdd2 to 2.0 v. changed note 16 of table 17 to a value of 2.0 v for vdd/avdd/avdd2. removed second sentence of the second paragraph in section 1.7.2, because it referenced information about a 1.8-v design. removed reference to 1.8 v in third sentence of section 1.7.7. 0.3 section 1.4.1.5: changed max-fp value for 33/133/266 of table 5, from 2.3 to 2.1 watts, to represent characterizaiton data. changed note 4 to say vdd = 2.1 for power measurements (for 2-v part). changed numbers for maximum i/o power supplies for ovdd and gvdd to represent characterization data. section 1.4.3.1: added four graphs (figures 5C8) and description for dll locking range vs. frequency of operation to replace figure 5 of rev 0.2 document. section 1.4.3.2: added row (item 11: t su sdram_sync_in to pci_sync_in timing) to table 9, to include offset change requirement. section 1.5.3: changed note 4 of pll_cfg pins in table 16 to note 20. section 1.7.2: added diode (mur420) to figure 27, voltage sequencing circuit. this is to compensate for voltage extremes in design. section 1.7.5: added sentence with regards to sdram_sync_in to pci_sync_in timing requirement (t su ) as a connection recommendation. section 1.7.8 : mention of t su offset timing, and driver capability differences between the mpc8240 and the mpc8245. 0.4 section 1.2: changed features list (format) to match with the features list of the mpc8245 integrated processor users manual . section 1.4.1.2 updated table 2 to include 1.8 100mv numbers. section 1.4.3: changed table 7 to include new part offerings of 333 and 350 mhz. added rows to include vco frequency ranges for all parts for both memory vco and cpu vco. section 1.4.1.5: updated power consumption table to include 1.8 v (vdd) and higher frequency numbers. section 1.4.3: updated table 7 to include higher frequency offerings and cpu vco frequency range. section 1.4.3.1: changed lettering to caps for dll_extend and dll_max_delay in graph description section. section 1.4.3.2: changed name of item 11 from t su sdram_sync_in to pci_sync_in time to t os sdram_sync_in to sys_logic_clk offset time. changed name to t os in note 7 as well. section 1.6: updated notes in table 17. included minimum and maximum vco numbers for memory vco. changed note 13 for location of pll_cfg[0:4] to correct bits location. bits 7C4 of register offset <0xe2>. added table 18 to cover pll configuration of higher frequency part offerings. section: 1.7 changed frequency ranges for reference numbers 0, 9, 10, and 17, for the 300 mhz part, to include the higher memory bus frequencies when operating at lower cpu bus frequencies. added table 18 to include pll configurations for the 333 mhz and the 350 mhz cpu part offerings. added vco multiplers in tables 17 and 18. section 1.7.8: changed t su sdram_sync_in to pci_sync_in time to t os sdram_ sync_in to sys_logic_clk offset time. section 1.7.10: added vendor (cool innovations, inc.) to list of heat sink vendors. table 19. revision history table (continued) revision no. substantive change(s)
56 mpc8245 integrated processor hardware specifications motorola document revision history 0.5 corrected labels for figures 5 through 8. 1.0 updated document template. section 1.4.1.4 changed the driver type names in table 6 to match with the names used in the mpc8245 users manual. section 1.5.3 updated driver type names for signals in table 16 to match with names used in the mpc8245 integrated processor users manual . section 1.4.1.2 updated table 7 to refer to new pll tables for vco limits. section 1.4.3.3 added item 12e to table 10 for sdram_sync_in to output valid timing. section 1.5.1 updated solder balls information to 62sn/36pb/2ag. section 1.6 updated pll tables 17 and 18 and appropriate notes to reflect changes of vco ranges for memory and cpu frequencies. section 1.7updated voltage sequencing requirements in table 2 and removed section 1.7.2. section 1.7.8updated trst inforrmation and figure 26. new section 1.7.2updated the range of i/o power consumption numbers for ovdd and gvdd to correct values as in table 5. updated fastest frequency combination to 66:100:350 mhz. section 1.7.9updated list for heat sink and thermal interface vendors. section 1.9changed format of ordering information section. added tables to reflect part number specifications also available. added sections 1.9.2 and 1.9.3. table 19. revision history table (continued) revision no. substantive change(s)
motorola mpc8245 integrated processor hardware specifications 57 ordering information 1.9 ordering information ordering information for the parts fully covered by this specification document is provided in section 1.9.1, part numbers fully addressed by this document. section 1.9.2, part numbers not fully addressed by this document, lists the part numbers which do not fully conform to the specifications of this document. these special part numbers require an additional document called a part number specification. 1.9.1 part numbers fully addressed by this document table 20 provides the motorola part numbering nomenclature for the mpc8245. note that the individual part numbers correspond to a maximum processor core frequency. for available frequencies, contact your local motorola sales office. in addition to the processor frequency, the part numbering scheme also includes an application modifier which may specify special application conditions. each part number also contains a revision code which refers to the die mask revision number. 1.9.2 part numbers not fully addressed by this document parts with application modifiers or revision levels not fully addressed in this specification document are described in separate part number specifications which supplement and supersede this document; see table 21. table 20. part numbering nomenclature xpc nnnn l xx nnn x x product code part identifier process descriptor package 1 processor frequency 2 application modifier revision level xpc 8245 l = standard spec. zu = tbga 266 300 l: 1.8/ 2.0 v 100 mv 0 to 105 c contact local motorola sales office (revisions a, b) xpc 8245 l = standard spec. zu = tbga 333 350 l: 2.0 v 100 mv 0 to 105 c contact local motorola sales office (revisions a, b) notes: 1. see section 1.5, package description, for more information on available package types. 2. processor core frequencies supported by parts addressed by this specification only. not all parts described in this specification support all core frequencies. additionally, parts addressed by part number specifications may support other maximum core frequencies. table 21. part numbers with separate documentation part number series operating conditions document order number of applicable specification xpc8245 t zu nnn x 2.0 v 100 mv, C40 to 105 c 266 mhz, 300 mhz, 333 mhz, 350 mhz mpc8245tzupns/d xpc8245 r zu nnn x 2.1 v 100 mv, 0 to 85 c 400 mhz mpc8245rzupns/d note: for other differences, see applicable specifications.
58 mpc8245 integrated processor hardware specifications motorola ordering information 1.9.3 part marking parts are marked as the example shown in figure 31. figure 31. part marking for tbga device tbga mpc8245l zu300c mmmmmm atwlyywwa 8245 notes : ccccc is the country of assembly. this space is left blank if parts are assembled in the united states. mmmmmm is the 6-digit mask number. atwlyywwa is the traceability code.
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mpc8245ec/d how to reach us: usa/europe/locations not listed: motorola literature distribution p.o. box 5405, denver, colorado 80217 1-303-675-2140 or 1-800-441-2447 japan: motorola japan ltd. sps, technical information center 3-20-1, minami-azabu minato-ku tokyo 106-8573 japan 81-3-3440-3569 asia/pacific: motorola semiconductors h.k. ltd. silicon harbour centre, 2 dai king street tai po industrial estate, tai po, n.t., hong kong 852-26668334 technical information center: 1-800-521-6274 home page: http://www.motorola.com/semiconductors document comments: fax (512) 933-2625 attn: risc applications engineering information in this document is provided solely to enable system and software implementers to use motorola products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. typical parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including typicals must be validated for each customer application by customers technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and the stylized m logo are registered in the u.s. patent and trademark office. digital dna is a trademark of motorola, inc. all other product or service names are the property of their respective owners. motorola, inc. is an equal opportunity/affirmative action employer. ? motorola, inc. 2002

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